Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

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News TSN Ethernet Subsystem Available from CAST Proven at IIC and LNI Plugfests

WOODCLIFF LAKE, NJ, USA, September 05 2018

A Time Sensitive Networking (TSN) subsystem for Automotive and Industrial Ethernet designed by Fraunhofer IPMS and available from semiconductor intellectual property provider CAST, Inc. has successfully undergone functional and interoperability testing at two recent multi-vendor plugfests in Germany: the Industrial Internet Consortium (IIC) TSN Plugfest July 24–27, 2018, in Stuttgart, and the Labs Network Industry 4.0 e.V. (LNI) Plugfest August 22–23, 2018, in Augsburg.

Scene from the LNI TSN Plugfest

Engineers from fifteen firms participate in the LNI Time Sensitive Networking Ethernet Plugfest in Augsburg, Germany August 22, 2018.

At these plugfests, engineers from Fraunhofer IPMS successfully added their reference design for a TSN end node device to an Ethernet network integrating TSN switches and endpoints from several independent vendors. The resulting TSN testbeds mimic real-world industrial and automotive environments with a diverse mix of real-time signal scheduling and priority challenges that must be satisfactorily managed by the system. The Fraunhofer IPMS design operated successfully, with respect to both its own functionality and in effective cooperation with the rest of each TSN testbed.

“Participating in these plugfests enabled us to rigorously exercise our TSN endpoint design in two different real-world-like environments, each networking our design with switches and end nodes from all the other leading TSN developers,” said Frank Deicke, business unit manager for Wireless Microsystems at Fraunhofer IPMS. “We found that our design performed extremely well and is definitely market-ready, while also gaining insights that will help our customers have even smoother TSN deployment experiences.”

About the Plugfests

Fraunhofer IPMS is a member of the Industrial Internet Consortium (IIC), and participated in the IIC TSN Plugfest that took place July 24–27, 2018, in Stuttgart, Germany. The testing there focused on two of the IEEE TSN standards: IEEE 802.1as Time Synchronization, and IEEE 802.1Qbv Time Aware Traffic Scheduling. Twenty firms contributed TSN designs, significantly enlarging the IIC TSN Testbed, which will serve as the foundation for future testing. Learn more about the IIC TSN program at www.iiconsortium.org/time-sensitive-networks.htm.

Fraunhofer also participated in the TSN plugfest conducted by Labs Network Industry 4.0 e.V. (LNI) on August 22–23, 2018, in Augsburg, Germany. Fifteen firms integrated their switch and end node designs across an Ethernet network for rigorous functional and interoperability testing. Learn more about LNI’s Ethernet TSN efforts at www.lni40.de.

About TSN and the Ethernet Subsystem

TSN subsystem block diagram

Block diagram showing the major elements of the TSN Ethernet Subsystem IP available from CAST.

The IEEE TSN Ethernet standards manage challenging networks having a mix of critical and non-critical nodes and have helped Ethernet emerge as the preferred bus for today’s complex industrial and automotive buses. TSN ensures that quality of service requirements are satisfied by prioritizing and scheduling diverse network traffic while also providing ultra-low and deterministically-constrained latency where needed.

Fraunhofer IPMS’ entry to the plugfests is a 1000 Mbps endpoint FPGA board based on a reference design for the TSN_CTRL Ethernet Subsystemalready available from CAST. That Subsystem combines three essential IP cores:

  • the Time Synchronizerimplements IEEE 802.1AS to automatically synchronize local and system time and generate timestamps and alerts needed for time-aware nodes and applications; 
  • the Traffic Shaperimplements IEEE 802.1Qav and 802.1Qbv to provide bandwidth allocation and time multiplexing for up to eight traffic classes, ensuring sufficiently low latency and minimum jitter as required; and 
  • a specially-designed Ethernet MACwith ultra-low latency provides standards-based Ethernet functionality that works well with TSN.

The company believes this is the first commercially-available IP subsystem implementing the latest TSN standards, and has already licensed it to multiple customers.

About Fraunhofer IPMS and CAST

The Fraunhofer Institute for Photonic Microsystems (IPMS) is a Dresden, Germany based research and development group focused on integrated circuits, microsystems (MEMS/MOEMS), nanoelectronicsand optical sensors and actuators. Learn more at www.ipms.fraunhofer.de.

CAST, Inc. is an experienced silicon IP supplier offering a range of compression solutions and image processing functions; 8051 microcontrollers and extreme-low-power 32-bit BA2X™ processors; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, straightforward licensing, and availability for ASICs or FPGAs from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300. 

CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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CAST is a trademark of CAST, Inc. BA2X is a trademark of Beyond Semicondictor. Other trademarks are the property of their respective owners.

 

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