Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

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News CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications

TSN Reference Design also available was used in live demonstrations of Ethernet Time-Sensitive Networking at DAC

DESIGN AUTOMATION CONFERENCE—SAN FRANCISCO, CALIFORNIA, USA, June 29 2018

Semiconductor intellectual property provider CAST, Inc. concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet.

TSN Ethernet Subsystem demo at 55th DAC

Editor John Blyler and CAST CEO Nikos Zervas discuss Automotive TSN Ethernet with the demo system at DAC.

TSN Ethernet has emerged as the preferred new bus for automotive and similarly challenging industrial applications. The new TSN_CTRL Ethernet Subsystem enables system designers to manage the ultra-low-latency communication and quality of service (QoS) attributes required for today’s increasingly sophisticated vehicles. It can, for example, ensure that a signal from obstacle avoidance sensors is given immediate processing with higher priority over competing signals from tire pressure sensors or the infotainment system, all without disturbing the critical network traffic related to engine or braking control.

The new TSN_CTRL Subsystem combines three essential IP cores to enable the high-precision timing synchronization and flexible yet accurate traffic scheduling needed to implement TSN Ethernet endpoints, bridges and switches:

  • a Time Synchronizer implements IEEE 802.1AS, automatically synchronizing the local time to the system’s (Grandmaster’s) time and generating timestamps and alerts needed for the development of time-aware nodes and applications; 
  • a Traffic Shaper implements IEEE 802.1Qav and 802.1Qbv, providing bandwidth allocation and time multiplexing for up to eight traffic classes to ensure sufficiently low latency (delay) and minimum jitter as required; and 
  • a specially-designed Ethernet MAC with ultra-low latency (delay) provides standards-based Ethernet functionality that works well with the Time Sensitive Networking.

The configurable TSN_CTRL IP implements a hardware subsystem that operates without software assistance once programmed. It communicates timing information to the system, and allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN_CTRL Subsystem uses standard AMBA®or Avalon®interfaces for straightforward system integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses.

A complete TSN Reference Design is available for evaluation or to jumpstart system design. It implements a network bridge receiving three types of traffic: 

  1. a video stream captured from an HDMI port, compressed with the CAST H.264 low-latency encoder core and streamed over RTP and UDP, 
  2. a “sensor” signaling every 100msec, and 
  3. a programmable “other traffic” generator emulating other types of traffic on the backbone.

Without TSN traffic shaping, the three sources compete for bandwidth, resulting in packet loss, dropped video frames, and considerable sensor signal jitter. But with TSN traffic shaping, bandwidth can be reserved per traffic source, and specific time slots can be assigned for the delivery of each traffic source. This allows, for example, the video to be delivered at its full bit rate and hence without any frames loss, and the sensor signals to be delivered with minimum latency and no jitter.

The TSN_CTRL Ethernet Subsystem is sourced from Fraunhofer IPMS. It is available now, in synthesizable RTL or as a targeted FPGA netlist. 

About CAST

In addition to the TSN Ethernet Subsystem and other leading automotive interface cores, CAST offers a range of compression solutions and image processing functions; 8051 microcontrollers and extreme-low-power 32-bit BA2X™ processors; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, straightforward licensing, and availability for ASICs or FPGAs from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300. 

CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

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CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners.

 

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