Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

News CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite

CAST’s JPEG-LS Encoder and Decoder provide a scalable, zero-latency, ultra-low-power hardware solution for numerically- or visually-lossless image compression

WOODCLIFF LAKE, NJ USA, June 12 2018

Semiconductor intellectual property provider CAST, Inc. has released a JPEG-LS Decoder IP core that—together with the JPEG-LS Encoder already available—provides an efficient hardware compression solution for the lossless or near-lossless transmission or storage of high quality images or video sequences.

The JPEG-LS cores provide:

  • Superior compression ratios, yielding smaller files than PNG and smaller or similarly sized files than JPEG 2000 (see figure);
  • Ultra-low power consumption, thanks to the low complexity of the JPEG-LS algorithm, which enables hardware implementations with an extremely small silicon footprint and minimal memory requirements;
  • “Zero” (sub-millisecond) latency, because the line-based processing employed by JPEG-LS does not impose any buffering of frames or even image lines before the encoding or decoding process is initiated; and 
  • Scalable throughput, uniquely handling ultra-high resolutions and/or frame rates by internally combining and managing a configurable number of parallel processing engines.
Chart: JPEG-LS yields better compression than PNG and similar or better than JPEG 2000.
Comparing the resulting file size and compression ratios of the PNG, JPEG 2000, and JPEG-LS lossless compression algorithms using typical images.
   
For example, consider the significant savings in hardware resources (16nm technology) possible for the lossless encoding and decoding of a 4K Ultra HD, 10-bit per color, RGB video stream at 30 frames per second: 
JPEG 2000 CAST JPEG-LS
several million gates
several Mbits of memory
more than 70mW 
tens of msec of latency
350K gates
300 Kbits of SRAM
 less than 10mW
less than 0.5 msec of latency

 

 

 

 

Moreover, the CAST JPEG-LS encoder will yield a similar or even better compression ratio as the JPEG 2000 encoder, resulting in further resource savings system-wide.

Their competitive compression ratio with smaller hardware and lower latency make the JPEG-LS Encoder and Decoder cores an excellent choice for systems where artificial intelligence or video analytics process the video stream—such as for autonomous driving or augmented reality applications—because these systems typically do not accept image quality loss or any extra latency, while also requiring very low power consumption. Additional applications include those requiring high quality images with maximum file size savings, including space and medical imaging (JPEG-LS is part of the DICOM medical imaging standard). 

About the JPEG-LS IP Cores

The JPEG-LS-E Encoderand JPEG-LS-D Decodereach fully support the JPEG-LS, ISO/IEC 14495-1 standard, which is based on the LOCO-I (LOw COmplexity LOssless COmpression for Images) algorithm developed by HP. The JPEG-LS-E has been used in products where decoding has been performed with standard software JPEG-LS decoders. The CAST Decoder appears to be the only such JPEG-LS decompression core commercially available; it can be used with the JPEG-LS-E or any other standard-conforming JPEG-LS encoder. 

The JPEG-LS cores are easy to integrate and use, employing standard AXI-Stream and APB interfaces and operating standalone without processor intervention once programmed. Each is available in two versions, size-optimized, and scalable-throughput. 

The single-pipeline, size-optimized versions process a single sample per clock cycle and require just one image line of buffering. The Encoder and Decoder can each handle several hundreds of Msamples per second when mapped to an ASIC technology; require as few as 40,000 ASIC gates; and run up to about 600 MHz and 350 MHz, respectively (on TSMC 16nm with SVT cells). 

The multiple-pipe, throughput-optimized versions internally aggregate a user-specified number of the single-pipeline cores, handling multiple samples each cycle to efficiently process images or video with ultra-high resolutions and/or very fast frame rates. This scalable throughput capability appears to be unique to the CAST JPEG-LS cores.

The silicon-validated JPEG-LS Encoder and Decoder are available now, with royalty-free licensing for either ASICs (RTL) or FPGAs (netlists) from popular silicon providers. 

About CAST

In addition to the JPEG-LS cores, CAST offers a range of compression solutions and image processing functions; 8051 microcontrollers and extreme-low-power 32-bit BA2X™ processors; industry-leading automotive interfaces; and a variety of peripherals, interfaces, security, and other IP cores. CAST IP features easy integration and reuse, royalty-free licensing, and availability for ASICs or FPGAs from all leading silicon providers. Learn more by visiting www.cast-inc.com, emailing info@cast-inc.com, or calling +1 201.391.8300. 

# # #

CAST is a trademark of CAST, Inc. Other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd, Suite 340, Woodcliff Lake, NJ 07677 USA • phone: +1 201.391.8300

 

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