Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Companion Cores
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
RTP Stack for H.264
RTP Stack for JPEG
• MPEG Transport Stream
  Encapsulator

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit product pages:

  • ZipAccel-C GZIP/ZLIB/Deflate Data Compression Core
  • GZIP-RD-A10 PCIe GZIP Compression Acceleration Card Reference Design

News CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem

WOODCLIFF LAKE, NJ USA, October 17 2017

A hardware accelerator that addresses the data compression and storage optimization needs of performance-critical data center applications is now available from semiconductor intellectual property provider CAST, Inc. This GZIP Accelerator Function is part of the expanded Intel® FPGA Design Solutions Network (DSN), of which CAST is an early member.

The CAST GZIP Accelerator integrates the popular ZipAccel-C™ GZIP/ZLIB/Deflate Compression IP Core with a PCIe interface, Direct Memory Access (DMA) function, and essential driver software in a high-performance, plug-and-play FPGA data compression system. Lossless data compression rates can exceed 40 Gbps, making the GZIP Accelerator an excellent choice for servers or database applications, where its data compression optimizes storage requirements or reduces network bandwidth needs.

GZIP-RD-A10 Block Diagram and Board

The CAST GZIP Accelerator (GZIP-RD-A10) IP implemented in an FPGA on the
Intel Programmable Acceleration Card (PAC).

The CAST GZIP Accelerator is now available as a ‘drop-in’ accelerator function for the Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA that is then added to servers. The Intel PAC card also pulls in frameworks and libraries using the Intel Acceleration Stack for Intel Xeon CPU with FPGAs, easing the use of FPGA acceleration.

“We’re seeing strong demand for our hardware GZIP data compression solution from data centers and other data-heavy or performance-critical applications,” said Nikos Zervas, chief executive officer for CAST. “Running this industry-leading GZIP accelerator on the Intel PAC with the Intel Acceleration Stack provides a significant win for customers needing faster data compression and decompression.”

“Intel is collaborating with a growing ecosystem of partners in our DSN program to bring new data center accelerator functions such as CAST’s GZIP data compression to our customers seeking options to accelerate workloads,” said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. “Customers and end users can benefit with faster time to market by using IP from CAST and the larger ecosystem built around our Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA.”

The CAST GZIP Accelerator is available now from CAST (www.cast-inc.com). Learn more about the accelerator function or the Intel FPGA DSN program at www.altera.com/dsn.

Intel, Xeon and Arria are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Zip-Accel is a trademark of Sandgate Technologies.

 

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