Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet pages:

  • CAMFE Camera Front-End Processor Core
  • H264-E-HIS H.264, High 10 Intra Profile Encoder Core

Visit Family of Video and Image Compression IP page:

News New Video Compressor and Camera Processor Cores Expand CAST’s IP Line

WOODCLIFF LAKE, NJ USA, January 18 2017

CAST, Inc. recently added two media processing cores to its extensive line of semiconductor intellectual property cores and subsystems.

  • The H.264-E-HIS High 10 Intra Profile Encoder Core is a low-power video compressor that rivals the quality produced by larger Motion JPEG2000 compressors and exceeds the quality of Motion JPEG compressors.
  • The CAMFE Camera Front-End Processor Core offers a flexible, resource-efficient means to convert the raw pixel data from a CMOS or CCD sensor to a video stream ready for display, processing, or compression.

“These new cores reflect our dedication to giving system designers a variety of sophisticated yet easy-to-use image and video IP options so they can choose and successfully implement the best technology for their specific application,” said Nikos Zervas, chief executive officer of CAST.

The High 10 Intra Encoder Core is an efficient intra-frame compression engine that supports the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. Suitable for applications needing moderate levels of compression, it produces Variable- or Constant-Bit Rate video that features high error resilience, allows for random access in the compressed stream, and eases video editing. It has a small silicon footprint—approximately 120K gates and 420K bits of SRAM—and requires no external memory (e.g. off-chip DRAM), allowing for very cost-effective and low-power ASIC or FPGA implementations.

The H264-E-HIS rounds out CAST’s comprehensive family of video and image compression IP, providing one of the best available choices for easily implementing compression and decompression for Internet of Things and many other applications. 

The CAMFE Camera Front-End Processor Core accepts the raw pixel output from an image sensor and produces standard RGB video ready for compression or other uses. The processor converts the Bayer pattern sensor output—via de-mosaicing interpolation and white balancing—and optionally optimizes the video with Contrast Stretching (Normalization), Gamma Correction, and Sharpening. Sourced from Ocean Logic, it adds to CAST’s line of graphics-related companion cores and subsystems that work alone or with compression IP.

Photos showing the image improvements made by the Camera Front End Processor (CAMFE) IP Core from CAST. with applications of Bayer Filter, White Balance, Contrast Stretching, Gamma Correction, and Sharpening Filter.

(Click to see a higher-resolution version.)

CAMFE image processing example.

The H264-E-HIS and CAMFE Cores are available now. Visit www.cast-inc.com or contact CAST Sales (info@cast-inc,com, +1 201.391.8300) to learn more.

 

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