Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

  • SHA-3 SHA-3 Secure Hash Function Core

News Accelerate SHA-3 Cryptographic Hash Processing with New Hardware IP Core

WOODCLIFF LAKE, NEW JERSEY, October 05 2016

A new intellectual property core supports the latest standard for protecting the integrity of electronic transmissions, Secure Hash Algorithm-3 (SHA-3), in a flexible, high-throughput, area-efficient hardware accelerator.  

SHA-3 Encryption IP Core from CAST, Inc.Developed by Beyond Semiconductor and available from CAST, Inc., the new IP core is compliant with the latest cryptographic standard from the National Institute of Standards and Technology (NIST)—FIPS 202—and the SHA-3 functions in FIPS 180-4.

One of the few IP cores supporting these standards, it offers competitively high throughput—up to 48 Mbits/MHz—and low silicon area—as small as 28K gates.

“Our hardware implementation of the SHA-3 algorithm gives developers a state-of-the-art cryptographic primitive with which they can harness the advantages of hardware-based security to protect their devices against current and future threats,” said Matjaž Breskvar, chief executive officer of Beyond Semiconductor. “While simply implementing cryptographic primitives is not enough to ensure device security, our efficient hardware implementation of the Keccak sponge function family presents a solid foundation for any secure, future-proof design.”

Designers can configure the new SHA-3 Secure Hash Function Core to provide an optimum solution for a variety of application challenges. The hash accelerator can implement any one of the fixed-length or Extendable Output (XOF) hashing functions that are provisioned by the standards: SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE-128, and SHAKE-256. Users can also trade off performance and silicon area in two ways: by opting for a sophisticated input buffering scheme that allows receiving the next input message while the previous message is being processed, and by altering the number of hashing rounds per clock.

SHA-3 Hashing Function IP Core Block Diagram

“Developers wishing to build the most secure, future-looking security into their devices and systems will want to consider using SHA-3,” said Nikos Zervas, chief executive officer for CAST. “This new core makes it easy to integrate SHA-3 hashing into a variety of products with aggressive performance and low-power requirements, and adds a new choice to our encryption cores family that helps developers boost security without requiring extensive cryptography knowledge.”

Availability and Licensing

The new SHA-3 core is available now in synthesizable RTL for ASICs or optimized netlists for FPGAs. Visit the CAST website (www.cast-inc.com) to learn more, then contact CAST to arrange an evaluation or discuss licensing (info@cast-inc.com, +1 201.391.8300).

To learn more about Beyond Semiconductor, visit www.beyondsemi.com, call +1 650.488.7413, or email info@beyondsemi.com.

About Secure Hash Algorithm-3

While the SHA-2 standard continues to be secure and is safe to use, NIST believes that SHA-3 provides a greater degree of future proofing against attacks. NIST began the search for a new hashing function algorithmically dissimilar to SHA-2 with the launch of an international competition in 2005. Of the 64 submissions, the winning algorithm, Kacaak, became the basis for the FIPS 202 SHA-3 standard. The new standard was approved on August 5, 2015.

Like other hash functions, fixed-length SHA-3 functions convert a digital message into a brief, fixed-length “message digest” that can act as a digital signature. Any change in the original message results in an easy-to-detect change in the digest, offering a degree of protection against purposeful or accidental modifications of the message. Hashing thus provides security for message authentication, and a check for data integrity in many electronic communication applications. The extendable-length XOF SHA-3 hashing functions allow developers to use these SHAKE algorithms as encryption ciphers, or as part of key derivation functions.

Because SHA-3 by design runs much more efficiently in hardware than other hashing functions, this new standard is considered an excellent choice for Internet of Things and other devices needing inexpensive, low-power circuitry but a high degree of security.

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