Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

  • CACHE-CTRL AHB Cache Controller Core
  • BA20 PipelineZero 32-bit Embedded Processor

News Cache Controller Core from CAST Augments Cache-Less 32-bit Processors

WOODCLIFF LAKE, NEW JERSEY, September 19 2016

A cache memory controller IP core available from semiconductor intellectual property provider CAST, Inc. brings cost- and resource-effective improvements in performance, bandwidth, and function to systems using cache-less 32-bit processors.  

Cache Controller IP core from CAST adds performance and features to systems with 32-bit processors.The new CACHE-CTRL Cache Controller IP Core enables the addition of single or multilevel cache memory to systems using cache-less 32-bit processors such as the BA20 PipeLineZero™ or ARM® Cortex®-M0 processors. This can significantly decrease the access time to energy-consuming DRAM, Flash, or EEPROM memories. It also allows these economical processors to run code directly from an off-chip NOR-flash device (Execute in Place, XIP) while minimizing the typical performance or power penalties of off-chip access.

The Cache Controller is easy to add to general purpose, digital signal processing (DSP), or application-specific instruction set (ASIP) processors in different types of embedded systems. It uses standard AMBA® AHB processor and memory interfaces, and supports clock gating. Mapping the core to any ASIC or FPGA technology is straightforward, as it has no special static RAM requirements and works with any standard, single-ported SRAM device.

The Cache Controller supports a four-way associative cache memory, and implements a Least Recently Used (LRU) replacement policy. Users can configure the number of cache lines and cache line width at synthesis time. The core is conservative in its use of silicon area; for example, when configured with eight words per line and 256 lines per set (1024 lines in total), it synthesizes to about 9,000 equivalent NAND2 gates. It also performs well—running over 1GHz in a typical 20nm technology—and has been silicon-proven.

Sourced from Silesia Devices, the new Cache Controller Core is available now from CAST. See www.cast-inc.com, email info@cast-inc.com, or call +1 201.391.8300 for more information.

All trademarks are the property of their respective owners.

 

tw    fbk    li    li    li
Top of Page