Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

News CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool

The two companies demonstrate a 30+Gbps high compression ratio GZIP accelerator running on a Xilinx-based FPGA platform that can be used as is or customized by developers without hardware expertise

SAN JOSE, CA — Flash Memory Summit, August 09 2016

Today, PLDA GROUP and CAST demonstrated the results of a tight collaboration to make FPGA-accelerated GZIP compression accessible to developers of data center applications. This collaboration leverages the QuickPlay™ Software Defined FPGA development flow with the integration of a high performance GZIP IP core from CAST. With this combination, software developers without any specific hardware or FPGA expertise can now develop their own FPGA-accelerated GZIP applications and achieve better performance and performance per watt over CPU-executed GZIP compression.

CAST ZipAccel GZIP compression demo FPGA board, easily developed with PLDA QuickPlayQuickPlay makes it easy to build the GZIP accelerator with a variety of data center boards using Altera® or Xilinx® devices. A live demonstration system can be seen running in the PLDA Booth (904) at the Flash Memory Summit 2016 in Santa Clara from August 9th to 11th.

Sharing the same vision of making FPGA-accelerated applications available to a large growing audience of non-FPGA experts, CAST and PLDA GROUP are delivering a complete FPGA based GZIP compression accelerator that can be further customized by developers without hardware expertise using the QuickPlay Software Defined development tool.

People are turning to the GZIP compression IP from CAST as it offers excellent features and performance. It provides full x86 compliance and is available in a wide range of configurations—from throughput-optimized versions delivering up to 40Gbps to compression ratio-optimized versions—and is customizable to fit specific customer requirements in terms of performance, latency, or footprint.

“The partnership with CAST has been fruitful and I am happy to see this first application come to life with this high quality GZIP core”, said Stephane Monboisset, marketing director for QuickPlay. “What is even more exciting is how developers can use QuickPlay to build their own custom GZIP accelerators, by adding additional processing or seamlessly modifying the I/O framework as they see fit. This enables use models beyond the traditional CPU accelerator, such as bump-in-the-wire and smart-NIC models with in-line compression of network and storage data.”

QuickPlay is a Software defined FPGA development tool that enables developers with different engineering backgrounds to model, design, debug, and deploy FPGA hardware as their end product or as a part of their final system, all without FPGA expertise, and without the pain and time traditionally associated with FPGA design. The availability of high-value IP such as the CAST GZIP compression core in QuickStore completely streamlines the integration in QuickPlay and offers a pay-as-you-go mechanism that enables users to pay for IP based on the number of implementations rather than a sizable upfront one-time fee.

“Building an FPGA-accelerated GZIP application is a non-trivial task when using traditional FPGA tools, and modifying it to fit specific customer requirements isn’t any easier” said Nikos Zervas, chief executive officer of CAST Inc. “Doing so with QuickPlay and enabling customers to customize it without requiring extensive hardware skills means that many more developers can benefit from the quality of our GZIP IP and build better FPGA accelerated applications with a complete Software Defined development flow.”

Product Availability:

The CAST ZipAccel™-C GZIP/ZLIB/Deflate Data Compression IP Core is available today in QuickStore. QuickPlay v2.1 is available today and supports numerous boards from various vendors. Log in or create an account at https://quickstore.quickplay.io to browse QuickStore and request a free, risk-free QuickPlay evaluation.

About QuickPlay

QuickPlay is a PLDA GROUP (www.pldagroup.com) brand that aims to accelerate the adoption of FPGA-based reconfigurable hardware in IT infrastructures by opening up FPGA design to non-hardware experts. QuickPlay is the result of years of research in the field of High-Level Design (HLD) and High-Level Synthesis (HLS) combined with PLDA GROUP strong expertise in FPGA hardware and IP design. QuickPlay enables leading technology companies to rip the benefits of FPGA without the pain, in domains such as Cloud computing, Vision, A/V broadcast, data center networking, HPC and more.

About CAST Inc.

CAST develops, integrates, and aggregates high-quality digital IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit processors; video, image, and data compression; automotive networking; and the peripherals, interfaces, security, and subsystems needed for the quick, low-risk development of system-on-chip designs. Visit www.cast-inc.com, or follow @castcores on Twitter.

QuickPlay and QuickStore are trademarks of PLDA Group. ZipAccel is a trademark of Sandgate Technologies. All other trademarks are the property of their respective owners.

 

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