Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Companion Cores
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
RTP Stack for H.264
RTP Stack for JPEG
• MPEG Transport Stream
  Encapsulator

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

News CAST Introduces Low-Power, Ultra-HD Capable Video Compression Cores

WOODCLIFF LAKE, NJ, July 21 2016

Semiconductor intellectual property provider CAST, Inc. recently introduced the newest generation in its eighteen-year-long series of IP cores for video and image compression.

JPEG IP Cores iconThe new 2016 Video and Image Compression Cores Family includes encoders and decoders covering a wide range of features and capabilities. Members of the family are each optimized for today’s most in-demand applications, from ultra-low-power for Internet of Things (IoT) devices; to cost-effective yet high-quality industrial vision and video streaming systems; through ultra-high-definition (UHD) and ultra-low-latency streaming allowing real-time video interaction in applications like remote surgery or drone control.

The new cores make it easier than ever for system designers to integrate video processing in superior yet less expensive products. Best-in-class features include:

  • Unmatched Performance/Size — Tiny silicon area requirements make the H.264 Video Compression Encoders half the size of most cores on the market, yet they’re still able to processes 4K UHD video in ASICs and higher-end FPGAs and Full-HD in lower-end FPGAs.
  • Highly Economical Video — The Motion JPEG cores offer compressed video quality that matches that of AVC/H.264, HEVC/H.265, and JPEG2000 encoders for the moderate compression levels practical for many applications, yet they require tremendously less power and silicon area and can operate without power-hungry off-chip memory.
  • Scalable Performance — The video encoders’ and decoders’ throughput can scale to readily handle 4K, 8K, or higher frame sizes and high frame rates even in modest FPGAs.

H.264 IP Cores iconThese hardware encoders and decoders operate much more efficiently than software or software/hardware codecs, saving considerable power over those options. They use industry-standard ARM® AMBA® AHB, AXI, and AXI-Stream interfaces, and they work in standalone mode, meaning once they are initially programmed they need no ongoing interaction from a system processor. The encoder cores are also quite flexible, and capable of either Constant (CBR) or Variable Bit Rate (VBR) operation.

These new media compression cores are revolutionary, providing video streaming capabilities in the lowest-cost, lowest-power silicon exactly when designers need more such capabilities for IoT and other rapidly growing product areas,”said Nikos Zervas, chief executive officer for CAST.“Never before, for example, could designers deliver 720p on an Altera® MAX 10, or 1080p on a Xilinx® Zynq®-7020, or full-duplex UHD/4K H.264 encoding and decoding in under 400K ASIC gates.

The AVC/H.264 Encoder Cores are optimized for low bit rates and low-latency video streaming. Adjusting quantization multiple times with a frame and using an artifacts-free intra-refresh coding method, these encoders produce CBR video streams of great video quality. The five encoders in the family provide low-power through ultra-fast AVC/H.264 single or multi-channel processing with support for different profiles. Also in the H.264 group are a surprising small matching decoder—occupying just 75K gates—and a fully-complaint Constrained Baseline profile decoder.

The JPEG Encoder and Decoder Cores include 8-bit Baseline and 12-bit Extended support, with variations aimed at low-power or high-performance operation. The cores are able to process JPEG Still-Image and Motion-JPEG payloads, and feature rate-control capabilities, which are essential for video streaming applications.

Completing the current family is an HEVC/H.265 Main Profile decoder that supports a wide range of video formats (i.e. 8 to 12 bit per color with 4:2:2 and 4:2:0 chroma subsampling) and is able to decode UHD/4K streams in high-end FPGAs and ASICs.

Though new to the CAST product line, all of the Video and Image Family Cores are mature and have been proven in customer products by our technology partners. The H.264 encoders and decoders are sourced from Ocean Logic, the HEVC/H.265 decoder from Fraunhofer HHI, and the JPEG encoders and decoders from Beyond Semiconductor.

The best way for potential customers to explore the opportunities of the new compression cores is to try them in-house. CAST makes this easy, with options from precompiled RTL models to bit-accurate simulation models through physical reference design kit boards. Contact CAST Sales to learn more.

Trademarks are the property of their respective owners.

 

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