Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Licenses GZIP Core to Tier 1 Wireless Chipset Vendor

CAST customer is using the GUNZIP IP core to save energy and resources via firmware compression within an LTE chipset.

Design automation Conference — Austin, TX, June 07 2016

AUSTIN, TEXAS — Design Automation Conference — June 7, 2016 — Semiconductor intellectual property provider CAST, Inc. today announced a recent sale of a GZIP data decompression IP core to a Tier 1 vendor producing wireless mobile communications chipsets.

The new customer is using the ZipAccel-D™ GUNZIP/ZLIB/Inflate Data Decompression Core to process compressed firmware stored in Flash memory on LTE chips primarily targeting the IoT market. This approach allows them to decrease energy consumption by reducing to less than half the number of accesses to the power-hungry Flash memory

Firmware compression like this works well because the decompression core CAST offers is fast and has a uniquely low latency—adding negligible delay to firmware processing in the chip—and is configurable to achieve the best trade offs of throughput, silicon area, and degree of data compression. Learn more about this novel in-chip application of GZIP compression in the CAST white paper ”Firmware Compression for Lower Energy and Faster Boot in IoT Devices.”

The sale also included CAST’s IP Integration Services, through which CAST’s experts handled fine-tuning of the core to create an optimum solution for the design without delaying the customer’s development schedule. This included balancing configuration options to yield an extremely small core implementation—under 40K gates—and developing a DMA-capable interface wrapper custom-tailored for efficient bandwidth utilization in the customer’s specific SoC architecture and bus fabric.

“Compression isn’t just for reducing the storage load in data centers or squeezing more in a wired or wireless communication link,” said Nikos Zervas, chief executive officer of CAST. “Savvy SoC designers are quickly discovering the power, bandwidth, and cost savings the ZipAccel compression cores enable inside of systems, and are delivering products their competitors just can’t match.”

The GUNZIP/ZLIB/Inflate Data Decompression Core is part of the ZipAccel family of data compression family CAST sources from partner Sandgate Technologies. A compression core and complete GZIP PCI-E Compression Reference Design Kit are also available. See www.cast-inc.com for more information.                                               # # #

ZipAccel is a trademark of Sandgate Technologies. All other trademarks are the property of their respective owners.
 

ZipAccel is a trademark of Sandgate Technologies. All other trademarks are the property of their respective owners.

 

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