Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

  • CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core
  • CANFD-RD CAN 2.0 & CAN FD Reference Design

News CAN FD Bus Controller IP Core Gains Time-Triggered TTCAN Capability

Available from CAST, Inc. this fully-featured soft CAN FD core supports all relevant specs, has Verification IP available, and will undergo its second Plug Fest in April

Nuremberg — Embedded World, February 23 2016

Semiconductor intellectual property provider CAST, Inc. today introduced standard support for the new Time-Triggered communication on CAN (TTCAN) protocol in the CAN Bus Controller IO Core it offers.

This CAN-CTRL CAN 2.0 & FD Controller Core, sourced from partner Fraunhofer IPMS, is among the few ASIC RTL and FPGA netlist cores to support TTCAN, the Flexible Data-Rate CAN FD protocol, and all popular CAN bus specifications:

  • CAN 2.0 and CAN FD — ISO 11898-1:2015 and earlier ISO, and Non-ISO (Bosch) versions
  • TTCAN — Time-Triggered CAN (ISO 11898-4 level 1)
  • Optimized support for the AUTOSAR and SAE J1930 specifications.

This CAN core was the first soft core to undergo rigorous testing at the CAN Open Plug Fest (in March 2015), and is scheduled for a second round at Detroit and Nuremberg Plug Fests in April and June respectively. Subsystem boards with the CAN-CTRL core and transceivers from ON Semiconductor and Microchip will be used in these strenuous evaluations.

Design verification for CAN-CTRL Core customers is facilitated through a partnership with verification IP expert Avery Design Systems. Developed independently but cooperatively, the Avery CAN 2.0 and FD VIP works “out of the box” with the core to provide smooth design and verification.

A ready-to-run reference design board and other development aids are also available from CAST to further shorten the time to market for CAN FD based systems. Visitors to Embedded World and DVCon (San Jose) are welcome to stop by the CAST booth for more information.

CAST, Inc. is a twenty-year-old developer, integrator, and aggregator of IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit Processors; video, image, and data compression; peripherals, interconnects and other functions needed for complete system designs. Visit www.cast-inc.com, or follow @castcores on Twitter.

 

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