Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses

CAN 2.0/FD controller
CAN FD Reference Design
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN Bus Master/Slave
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security

Encryption Primitives
AES, Programmable
Key Expander
Single, Triple

Hash Functions
SHA-3 (Keccak)

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

  • UHT-JPEG-E Ultra High Throughput JPEG Encoder Core

News Ultra-High Definition Video Encoding Now Feasible in Low-Cost FPGAs or Low-End ASICs

Woodcliff Lake, NJ, April 28 2015

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

A new hardware encoder has the performance and efficiency needed to make 4K, 8K, or very high frame rate HD video output viable for low-volume or cost-sensitive products.

This new Ultra-High Throughput (UHT™) JPEG Encoder IP Core available from semiconductor intellectual property provider CAST, Inc., is sourced from semiconductor IP company Alma Technologies. The core uses a high-performance, scalable, parallel-processing architecture to efficiently handle the significant pixel processing demands of advanced video encoding. This makes it one of the few available solutions for processing ultra-high definition (UHD) video—or very high frame rate standard or high definition video—in low-cost FPGAs or lower-end ASIC silicon.

For example, from common 422 format video input, the new encoder can:

  • Process more than 1 Gpixels/sec in the lowest speed graded devices in the Altera® Cyclone® V or Xilinx® Artix®-7 FPGA families, and
  • Process over 10 Gpixels/sec on a TSMC® 40nm LP process.

To encode 4K Ultra-HD video (2160p at 30 frames per second), the core needs as few as 30K Logic Elements in Altera Cyclone V devices, 40K Logic Cells in Xilinx Artix-7 devices, or 300K gates in a TSMC 40nm LP ASIC. 

“The silicon economics of UHD encoding via this new core make it feasible to deliver 4K or 8K video in classes of products for which HEVC H.265 high-def encoding is too complex and expensive,” said Nikos Zervas, chief executive officer of CAST. “The new encoder also satisfies embedded system designers’ requirements for many industrial, defense, and other applications, as it makes it more cost-effective than ever to encode standard- and high-definition video at the very high frame rates needed for these systems.”

About the UHT JPEG Encoder Core

The UHT-JPEG-E Ultra-High Throughout JPEG Encoder Core is a standalone hardware encoder that works independently of a system’s host CPU (after its initial programming) and complies with the 8-bit Baseline and 12-bit Extended Sequential JPEG standards (ITU T.81 and ISO/IEC 10918-1).

UHT-JPEG-E Block Diagram - encode motion 4K video in inexpensive FPGAs and ASICs

The Ultra-High Throughput JPEG Encoder IP Core efficiently handles 4K and greater resolution video with a scalable, high-performance, parallel-processing architecture.

The encoder employs a scalable architecture of multiple parallel processing units to achieve a class-leading encoding rate of up to 32 samples per clock cycle. It splits an incoming still image or video frame into chunks and assigns each to a processing unit automatically, without intervention from or demand on the host system. Users can configure the maximum number of parallel processing units to be implemented—fine tuning this to best exploit the target technology—and all non-critical resources are automatically shared among the multiple processing units to reduce silicon area.

The core’s raster scan input accepts all popular formats, i.e., 4:4:4, 4:2:2, 4:2:0 and 4:0:0 chroma sampling, in 8, 10 or 12 bits per component sample depth. It produces a complete JPEG byte stream, which can be processed for playback by any standard-complaint decoder and is suitable as JPEG payload in Motion-JPEG streams.

These streaming interfaces for the pixel input and compressed stream output—plus a microprocessor-like interface to its registers and optional AMBA AHB or AXI bus wrappers—help make the Encoder easy to integrate in any System on Chip (SoC) design. For further flexibility and economy, the Encoder’s external memory interface is independent of memory type and can work with either on-chip SRAMs or off-chip DDR memories, while its tolerance of memory latency makes the Encoder suitable for shared-memory architectures.   

Users of the Encoder can readily balance its JPEG quality factor versus the bit rate of its output stream. An optional Constant Bit Rate (CBR) mode makes the Encoder suitable for a wide range of video streaming applications, as it allows real-time control over the compression ratio as well as the end-to-end latency, via regulation of the transmission buffer size. 

The Ultra-High Throughput (UHT™) JPEG Encoder IP Core is available now. A bit-accurate model plus extensive pre-sales support is available to help potential customers fully evaluate the Encoder before purchase. Call CAST at +1 201.391.8300 or email for more information.

About Alma Technologies

Alma Technologies is a semiconductor IP company, offering high-quality IP cores since 2001. Its products stand out for their engineering, being complete, easy-to-use and reliable IP solutions. Alma Technologies IPs are backed by best-in-class technical support and they are proven in a long track record of over 200 licensees’ designs. Learn more at

About CAST

CAST is a twenty-year-old developer, integrator, and aggregator of IP cores for ASICs and FPGAs. The company offers some of the best available choices for low-power, high-value IP, including 8051s and BA2x 32-bit Processors; video, image, and data compression; security, interfaces and other functions needed for complete system on chip designs. Visit, or follow @castcores on Twitter. 

UHT is a trademark of Alma Technologies. Other trademarks are the property of their respective owners.


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