Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet page:

  • H265-MP-D Main Profile Intra HEVC Decoder Core

News Full-Hardware Real-Time H.265 HEVC Video Decoder Core Coming from CAST

San Francisco, CA — Design Automation Conference, June 02 2014

Semiconductor intellectual property provider CAST, Inc. is demonstrating here at DAC a new, high-performance, low-power, full-hardware H.265 video decoder core that handles next-generation video steams in real time without need for software computations running on a central processing unit (CPU). The new H.265-MP-D Main Profile Intra HEVC Decoder Core is the first in a series of H.265 High Efficiency Video Coding cores CAST will offer, and will be available in the third quarter of this year.

The H.265-MP-D is sourced from the Fraunhofer Heinrich Hertz Institute (HHI). Fraunhofer engineers participated in the standards effort leading to H.265 HEVC, and the core fully conforms to the resulting ISO/IEC 23008-2 HEVC and ITU-T H/265 industry standards. Fraunhofer HHI is also one of the few—and among the most highly-respected—sources for the complete H.265 compliance test streams used throughout the industry, and the core has been rigorously verified using them.

The decoder design is distinguished by clever use of internal and external memory. Its application-specific internal memory architecture enables reuse of already fetched data, which keeps more memory transfers within the chip to yield lower external memory bandwidth and power consumption. It also has a high tolerance to memory latency (delay), which is critical when expensive external memory is shared with other blocks such as a CPU.  These benefits—coupled with the decoder’s full-hardware, CPU-less decoding ability—make the core a great match for any applications requiring real-time H.265 performance but having power, packaging, or budgetary constraints.

The H265-MP-D HEVC Video Decoder Core joins CAST’s line of MCUs and MPUs, image and video compression codecs, GPUs and graphics accelerators, and other IP cores and subsystems for building competitive FPGA and ASIC systems. To learn more, call +1 201.391.8300, visit www.cast-inc.com, or follow @castcores on Twitter.

 

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