Woodcliff Lake, NJ, May 30 2014
Continuing to use the hundreds of thousands of old systems built around 8051 microcontroller chips has become easier and highly cost-effective with a flexible new 8051 IP core available from semiconductor intellectual property provider CAST, Inc.
The L8051XC1 Legacy-Compatible 8051 IP Core combines modern MCU design techniques with easily-modified architectural timing and peripheral sets in an MCS8051 code-compatible core for FPGAs or ASICs. Built on a modern base design that performs as fast as one clock cycle per instruction, versions of the L8051XC1 core can exactly match the timing of existing chips with twelve-, six-, or four-cycle-per-instruction architectures. The default peripherals bundled with the L8051XC1 exactly match those of the original Intel 8051 MCU chip, but other bundles drawing CAST’s broad library of IP cores are also available.
The new core offers a uniquely effective solution for maintainers of legacy systems by enabling exact code and timing compatibility for new system-on-chip (SoC) designs implemented in FPGAs or ASICs. In some cases new supplies of an 8051 chip on a board might be unavailable; in others several existing boards might be combined in a more compact, energy-efficient, and less expensive to produce single FPGA. Because legacy systems often incorporate application expertise that would be difficult and expensive to replace today—such as the many specialized industrial, military, and medical products built around old 8051 chips—it is critical that new versions conform to old specifications down to a thousand of a millisecond.
Sourced from Silesia Devices, the twelve-cycle version of the L8051XC1 is shipping now, with a standard peripherals set and full development and debugging aids. Different peripherals and architectures are available on request.