Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

News CAST Introduces H.264 Video Over IP Subsystem to Simplify Video Streaming Product Development

Woodcliff Lake, NJ, October 10 2013

Semiconductor intellectual property provider CAST, Inc. has released a reusable subsystem and suite of hardware reference designs that make it easier to build video streaming into mobile and other products.

The new H264OIP-HDE Subsystem integrates three IP cores available from CAST: the H.264 High Profile Video Encoder (H264-HP-E) core for high-quality video compression, and the RTP and UDP/IP hardware stacks for encapsulating video for Internet Protocol transmission. Flexible video, memory, and network interfaces simplify system integration, and optional logic blocks enable standalone, processor-free subsystem operation. Available hardware reference design systems provide a turnkey jumpstart to streaming system development.

The new subsystem is an especially competitive solution for low-latency applications that demand minimal video delay. The advanced rate control capabilities of the H.264 encoder core, the near-zero latency of the hardware RTP/UDPIP encapsulation, and the ability to directly process the uncompressed video stream as presented by the capturing device together enable the H264OIP-HDE Subsystem to stream video with ultra-low—sub-5ns—latency. Furthermore, the subsystem’s dedicated hardware implementation means it consumes significantly less energy than any similar software-based alternative.

“This new video over IP subsystem makes the superior H.264 compression we offer drop-in ready for high-performance, low-latency, low-energy, video streaming over Ethernet or Wi-Fi,” said Nikos Zervas, chief operating officer for CAST. “Completing the solution are FPGA reference designs for turnkey HDMI- or DVI-to-Ethernet streaming in hardware, and customization services through which we can deliver a pre-packaged and fully-verified combination of any video-in or network controllers a customer requires.”

Reference designs for the streaming subsystem are available now for the Altera® Stratix® IV and Arria® V families, and the Xilinx® Kintex®-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.

CAST’s IP customization services are available to integrate the Subsystem with a variety of memory controllers, input video interfaces (e.g., DVI, HDMI, MIPI-CSI, or SDI), and IP-based MAC controllers (e.g., Ethernet or 802.11 Wi-Fi). Other options include multiple video channels, different video preprocessing modules, or different compression algorithms (e.g., JPEG or JPEG 2000), and mapping the subsystem to different FPGA platforms.

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

The H264OIP-HDE Subsystem in RTL for ASICs or netlists for FPGAs is available now, including the H.264 Encoder Core (sourced from Alma Technologies SA) and the CAST RTP and UDP/IP Cores, other essential functions, complete documentation, and more. Call CAST at +1 201.391.8300 or visit www.cast-inc.com for more information.

 

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