Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit product page:

  • UDPIP UDP/IP Hardware Protocol Stack Core

News CAST Adds Multicast and AXI to UDP/IP Core for Streaming Media Systems

Woodcliff Lake, NJ, February 19 2013

Semiconductor intellectual property provider CAST, Inc. has improved its UDP/IP Hardware Stack IP core with customer-requested features that make it even more effective for processor-less streaming of audio or video over Ethernet.

The User Datagram Protocol (UDP) is a transport layer communications standard within the Internet Protocol suite that is simpler and quicker than Transmission Control Protocol (TCP/IP). This makes it better for video or audio media streaming over the Internet or within a private network; the GigE Vision, ONVIF, and PSIA standards for IP-based cameras, for example, all incorporate UDP.

CAST's hardware UDP stack core handles the millions of instructions per second that a host processor would otherwise spend on UDP framing and checksum validation. The new version supports IP multicast for delivery of a single source’s data to multiple receivers using the IGMPv3 standard, and it adds an interface to the AMBA® AXI4 bus for easier integration of UDP in high-performance systems.

“Our UDP stack core is one of the smallest available,” said Tony Sousek, an IP development manager at CAST. “Now with IP multicast and AXI4 bus support, the UDPIP partners perfectly with our compression codecs and Ethernet MACs to more efficiently handle streaming media for Internet television and other popular applications.”

The improved UDP/IP Hardware Core Stack is available now, alone or integrated with an Ethernet MAC core from CAST, Altera, or Xilinx or with any of CAST’s video and image compression cores. Call CAST at +1 201.391.8300 or visit www.cast-inc.com for more information.

 

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