Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Learn more about

News JPEG Encoder IP Core from CAST gets Rate Control Options, Faster FPGAs

Woodcliff Lake, NJ, June 04 2012

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

Semiconductor IP provider CAST, Inc. today announced functional and performance improvements for the JPEG Encoder IP core it provides.

System designers now have a choice of two rate control options that allow application-specific tuning of the JPEG compression function:

  • Buffer-Limited, Block-Based Rate Control minimizes on-chip memory for buffering and transmission bandwidth with good-quality image results.
  • Motion JPEG Video Oriented Rate Control maximizes the quality of results for Motion JPEG streams, while still using hardware resources efficiently.

“Image compression simply means ‘JPEG’ to the uninitiated, but this is very far from a ’one size fits all’ technology,” said Nikos Zervas, vice president of marketing for CAST. “The specific compression algorithm and the choice of processing options within it can make a huge difference on quality, bandwidth, memory requirements, performance, and energy consumption. We pride ourselves on helping customers understand, determine, and deploy the optimum encoder for their particular system.”

The JPEG Encoder core now runs on the latest Altera® and Xilinx® FPGAs, at up to 400 MSamples/sec. This means a single encoder core can process 1080p@60fps video on low-cost Altera Cyclone-V and Xilinx Artix™-7 devices, or Digital Cinema 4k@30fps on higher-end devices like Altera Stratix® V and Xilinx Virtex®-7 FPGAs. The core has also been tested with the new Xilinx Vivado™ toolset, for better productivity when working with Xilinx devices.

CAST offers and supports the broadest and deepest set of image compression IP cores and subsystems available, including JPEG, Scalado Speedtags JPEG, 12/8-bit Extended JPEG, lossless LJPEG and JPEG-LS, and JPEG 2000. Video compression cores from CAST include multiple H.264 profiles, MPEG2, and DV. The JPEG and H.264 IP cores are sourced from Technology Partner Alma Technologies.

See the full line with datasheets at www.cast-inc.com/ip-cores/images, or learn more by calling +1 201.391.8300, or emailing info@cast-inc.com.

 

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