Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Visit Product Datasheet pages:

  • UDPIP Hardware UDP/IP Stack Core

News CAST Full Hardware UDP/IP Stack Core Simplifies Streaming Media Over IP Networks

Woodcliff Lake, NJ, December 15 2011

A new core from semiconductor intellectual property (IP) provider CAST, Inc. the UDPIP, provides an extremely competitive hardware implementation of the User Datagram Protocol (UDP), part of the Internet Protocol Suite (TCP/IP) for data transfer over Ethernet.

UDP is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). This makes UDP good for applications like video or audio streaming, where receiving most of the data packets on time matters more than receiving every single packet. For example, the GigE Vision, ONVIF, and PSIA standards for IP-based cameras all incorporate UDP.

Implementing the UDP/IP stack in hardware saves millions of instructions per second that a host processor otherwise spends on UDP framing and checksum validation. Furthermore, UDP’s direct, processor-free connection to media encoders and decoders eliminates the need to temporarily store streaming media data, significantly simplifying bus and memory arbitration, lowering design complexity, and reducing power consumption for streaming-capable SoCs.

The CAST UDPIP core supports a superset of typical UDP/IP functions (details below) and is configurable for transmit, receive, or both (full-duplex). It works with any 10/100/1000 Mbit Ethernet MAC transceiver, including FPGA MACs from Altera® and Xilinx® and synthesizable versions such as the CAST MAC-1G core. Performance suitable for 10 gigabit Ethernet (10GbE) has been achieved in some ASIC implementations. Integrating the core in system-on-chip designs is made easier through support for industry-standard streaming and bus interfaces.

Silicon implementation results indicate this is one of the smallest available such cores. For example, it uses just 1,000 slices for the receive function on a Xilinx Virtex-5 device. (See more sample results online.)

UDPIP Core Features & Availability

CAST designed the core to operate without need for a processor and to handle any likely UDP and streaming media requirements.
The core transmits and receives UDP packet data messages to one (unicast) or more (broadcast) targets on an Ethernet LAN, using IPv4 without packet fragmentation (DHCP support is optional). It generates and validates outgoing and incoming checksums; Ethernet CRC error correction is an option.

Trouble-free network operation is ensured via run-time programmable parameters (IP and MAC addresses, ports) and both the critical for multiple-access networks ARP (Address Resolution Protocol) and Ping (the Echo Request and Reply Messages of the Internet Control Message Protocol, ICMP) for testing network connectivity.

The core can connect directly to media codecs via dedicated streaming-capable interfaces or via an arbitrated system bus. Available interfaces include AMBA AXI4-Stream and Avalon®-ST for streaming packet data, and the AMBA AHB, Avalon-MM, and Wishbone system bus interfaces.

The CAST UDPIP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available, to make it even easier for SoC designers to incorporate video streaming over IP networks.

About CAST, Inc.

The UDPIP core is part of CAST’s continuing, 18-year-long commitment to provide the best IP products—and the best experiences using them—available anywhere. The diverse, proven CAST product line features 32-bit processors and 8-bit microcontrollers; advanced image/video compression and processing cores; and the memory controllers, high-speed buses, peripherals, and other functions needed to build complete systems.

These are all backed by CAST’s worldwide team of sales, support, and development experts, who pursue customer success with a devotion—and a reputation—unmatched in the industry.

Learn more by calling +1 201.391.8300.

CAST is a trademark of CAST, Inc., Other names may be trademarks of their respective owners.

 

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