Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

H264-AP CAST Application Platform Simplifies H.264 Video Compression Evaluation and Analysis

News CAST Application Platform Simplifies H.264 Video Compression Evaluation and Analysis

Woodcliff Lake, NJ, May 25 2010

H264-AP formeraly named H264-REF.

Electronic system design engineers who need to understand and evaluate H.264 video encoding now have a quick, cost-effective, ready-to-run tool for doing just that.

The H264-AP H.264 Video Encoding Application Platform from semiconductor intellectual property (IP) provider CAST, Inc. combines multiple hardware functions and essential software in a pre-integrated, well-documented package. The System is available now, running in either Altera or XIlinx FPGAs on commercial prototyping boards.

http://www.cast-inc.com/application-platforms/h264-ap/index.html

The heart of the system is the H264-E Encoder Core developed by Alma Technologies S.A. This core produces high quality compressed video at up to 1080p resolution and 30 frames per second. It uses an efficient Baseline Profile architecture, and processes video with less latency and fewer hardware resources than many competing cores.

The H264-AP Platform also includes a PCI Express Endpoint Controller Core, an H.264 Multimedia Interface Core, and an appropriate DDR Memory Controller Core.

Custom H264-AP software provides a graphical user interface that makes it easy to control H.264 encoding parameters such as the target quality level or a constant bit rate requirement. The GUI also helps a designer manage workflow details like input and output clip specifications. The system includes additional drivers and other software to make it ready to run as delivered.

The cores are implemented in either Altera or Xilinx FPGA systems: the Altera Stratix IV GX FPGA Development Kit includes a fast grade Stratix IV silicon device, and the V5 TAI Logic Module Virtual FPGA Prototyping System from S2C, Inc. includes a fast Virtex-5 device.

CAST has been offering H.264 IP cores for over five years as part of one of the broadest available multimedia IP product lines.

"The H264-AP Platform satisfies two customer needs we've frequently seen," said Bill Finch, senior vice president. "Many products require H.264 video encoding, but designers have little or no experience with this complex compression technology, and need an easy platform for learning and experimentation. Moreover, any designer considering H.264 IP should evaluate the actual core with multiple samples of their own video material, in an environment where they can replicate the conditions anticipated for their system."

The H264-AP Platform was recently licensed by CARERI, the Chinese Aeronautical Radio Electronics Research Institute, for use in the CAST IP Joint Lab established at CARERI's facility in Shanghai, China.

A new J2K-REF Reference Design System will soon join the H264-AP, using the same platform to bring similar evaluation and analysis benefits to the complex JPEG 2000 image compression standard.

To see a live demonstration of the H264-AP System, visit CAST at DAC, the Design Automation Conference in Anaheim, CA, June 13-15, 2010, booth 521. For more information, please visit or contact CAST: www.cast-inc.com, sales@cast-inc.com, +1 202.392.8300 See also CAST partner sites: Alma Technologies, S.A. — www.alma-tech.com S2C, Inc. — www.s2cinc.com

CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.

 

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