Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News SoC Solutions Builds FPGA System in Record Time Using Synopsys’ ReadyIP Flow and CAST IP Cores

Woodcliff Lake, NJ, June 04 2008

Silicon Intellectual Property (IP) provider CAST, Inc. and technical partner SoC Solutions LLC recently proved the effectiveness of a new FPGA design capability from Synopsys’ Synplicity Business Group by developing a complete 32-bit processor-based system in just three and a half days.

The system is a typical design that uses an ARM® Cortex™-M1 processor and includes all the buses and peripherals needed to run embedded software. SoC Solutions’ engineers estimate it took them less than half the time if would normally have taken them to create the system, which they demonstrated recently at the Embedded Systems Conference (ESC).

The quicker development was made possible by Synopsys’ new ReadyIP initiative for technology-independent FPGA design. This includes the ReadyIP line of pre-packaged, pre-licensed evaluation  cores—supplied by CAST and others—and the new System Designer capability included in the Synplify Pro® and Synplify® Premier FPGA implementation tools, that makes it easy to define and synthesize FPGA systems.

“Our experience with ARM processor-based systems and the IP infrastructure needed to make them work certainly helped, but the real advantage behind our fastest system development ever came from Synopsys’ new ReadyIP program,” said Jim Bruister, president of SoC Solutions.

 “FPGA designers for the first time have an independent system integration tool flow with easy access to popular third-party IP like that from ARM and CAST, that works across all FPGA vendors,” said Bruister. “Companies now have a real opportunity to evaluate their designs using different FPGA vendors, and to easily migrate their entire systems between FPGAs and ASICs.”

Using the ReadyIP Program

Synopsys’ ReadyIP program offers the first practical ability to easily acquire and integrate evaluation IP from multiple independent providers and target it to devices from multiple FPGA vendors.

Suppliers using the ReadyIP flow ensure consistent packaging and interconnection compatibility across the ReadyIP program by using the SPIRIT Consortium’s IP-Xact metadata format. Their valuable IP is protected using the encryption technology with digital rights management (developed by the Synplicity Business Group of Synopsys and now undergoing standardization in the IEEE's P1735 Working Group). Vendors offer their cores through ReadyIP under simple, click-to-agree evaluation licenses, eliminating the red tape typically surrounding IP use and making possible the “push-button downloads” philosophy behind the ReadyIP program.

FPGA designers use a new IP browser built in to Synopsys’ Synplify Pro and Synplify Premier tools to select and download ReadyIP partner cores, then use the System Designer tool to connect and configure the ReadyIP cores along with their own internal IP. Designers synthesize the resulting system to a target FPGA, and then evaluate their design and their FPGA decisions. Only when satisfied and ready for production do they need to purchase commercial licenses from the ReadyIP Program’s core suppliers.

“The success that SoC Solutions achieved by using the new ReadyIP flow and System Designer capability is a testament to the fact that our standards-based tools simplify IP access and use,” said Angela Sutton, product marketing manager, Synopsys Synplicity Business Group. “This technology, which is included in our Synplify Pro and Synplify Premier tools, provides embedded systems designers with an extremely productive path to implementing complex systems in FPGAs.”

Implemented on a Synopsys HAPS-51 high-speed prototyping system, the ESC demo system ran a live software debugging session complete with two-way communication with a laptop PC through a Hyperterm window.  The demo exercised the ARM Cortex-M1 processor and a comprehensive set of AMBA buses and peripherals, including the AHB and APB buses, an AHB to APB Bridge, Memory Controllers, Timer, UART, GPIO, PWM, and external FLASH and SRAM memories.

The system infrastructure library used in the demo system — called the PiP-AMBA — was developed by SoC Solutions and is part of the CAST product line. ReadyIP charter member CAST provided the greatest number of downloadable cores at the launch of the program, with samples from CAST’s broad line of IP including a JPEG encoder and decoder, PCI Express controllers, an SDRAM memory controller, and other interface and communications functions.

More information is available on the web:

About Soc Solutions

SoC Solutions provides solutions for microprocessor based FPGAs, ASICs, ASSP, and Structured ASICs.  SoC Solutions was founded in 2000 by experienced ASIC and Embedded Software designers with a rich history of designing ASICs with embedded microprocessors.  Our Pre-integrated IP Platforms have been used successfully in numerous ASICs, FPGA and Structured ASIC designs.  SoC Solutions is located in the Atlanta Georgia area.

About CAST, Inc.

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

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