Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

Datasheets

News CAST Expands Image Compression Line with New JPEG-LS Encoder Core

DATE Conference, Nice, France, April 16 2007

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced that it has expanded its family of image compression IP products with a new lossless compression core using the JPEG-LS standard.

The company believes that this is the only commercially-available JPEG-LS IP core. This addition makes CAST’s family of JPEG cores the most complete from any single vendor, featuring a mix of encoders, decoders, and codecs for the JPEG, lossless JPEG, JPEG-LS, and JPEG 2000 standards.

The JPEG cores are developed by CAST partner Alma Technologies, S.A. in Athens, Greece (www.alma-tech.com). Most have been silicon-proven with multiple customers, in applications ranging from JPEG for ultrasound topographers and cellular phone chipsets to JPEG2000 for satellites and LJPEG in high-end digital SLR cameras.

The new JPEGLS-E Encoder Core implements the ISO/IEC 14495-1 JPEG-LS standard. This low-complexity algorithm is designed to efficiently compress continuous tone color and grayscale images (i.e., photos) with lossless and near-lossless levels of quality. The core itself offers a compact physical size and unusually-high processing rate—up to 161 MSamples/second on an FPGA, enabling HDTV processing—and has automatic and programmable features that simplify system integration.

Compared with lossless JPEG, the JPEG-LS core offers a higher compression level (smaller files) with a similar physical size. Compared with JPEG 2000’s lossless mode, it provides equivalent or greater compression with much smaller hardware.

The new core is available immediately, in HDL source code for ASICs or optimized netlists for structured ASICs and FPGAs. See www.cast-inc.com/jpegs for technical details, plus JPEG family datasheets, output image comparisons, and tips for choosing the best compression core for any particular application.

About CAST, Inc.

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia. See www.cast-inc.com for more information.

CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.

 

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