Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Expands Memory Controller Line with IP Core for DDR2 SDRAM Devices

Santa Clara, California, January 30 2007

The DDR2-SDRAM-CTRL core has been discontinued. Please contact Sales to learn more.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced a new IP core that implements a controller for all industry-standard DDR and DDR2 memory devices.

The new DDR2-SDRAM-CTRL IP core handles the interaction between SDRAM chips or DIMMs and the processor or a DMA in a system using that memory. The core significantly simplifies memory management challenges for the developer, implementing all the necessary data management, initialization, and address, and burst handling operations.

A high-performance, pipelined and parallel architecture featuring a three-stage processing queue is designed to always get the most out of available system bandwidth. A clever core architecture splits the system interface into separate control, write-data, and read-data paths for easier integration and faster operation. Flexibility is ensured by making all memory parameters runtime-configurable, including timing, memory size, mobile-SDR support, and auto-refresh policies. Power-saving features include power down and self-refresh modes.

Integration of the core is made easier for developers by delivering it with everything needed to for immediate use: one of two different PHY physical device layers and data path queuing elements (FIFOs). The core itself is available in HDL source code, or as an optimized netlist for FPGAs and structured ASICs.

Initial implementations of the core show it to be competitive in performance and area. For example, it achieved 262 MHz with under 1500 LUs in an Altera Sratix II, and 266 MHz with under 1300 slices in a Xilinx Virtex-4. These figures include the FIFOs and other elements not typically offered within a DDR controller core.

The new core was developed by CAST partner Alma Technologies, based in Greece (see www.alma-tech.com). It joins the other cores in CAST’s memory controller line: SDR-SDRAM-CTRL for single data rate mobile SDRAM devices, and NFlashCtrl for NAND flash memory devices.

About CAST, Inc.

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

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