Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Visit the eASIC site to learn more.

eASIC

News eASIC Teams with CAST to Deliver ARM926EJ AMBA Compliant Peripherals for 90nm Nextreme™ Structured ASICs

CAST joins eASIC’s newly established eZ-IP Alliance program

Santa Clara, California, January 11 2007

eASIC Corporation, a provider of Structured ASIC devices and Configurable Logic IP, today announced the availability of  ARM AMBA Platform IP (PIP-AMBA-E) from CAST for eASIC’s 90nm Nextreme Structured ASIC product family. CAST, who joined the company’s newly established eZ-IP Alliance program, will partner with eASIC to provide customers with the essential IP cores and software infrastructure for eASIC’s soft ARM926EJ microprocessor core.

The PIP-AMBA package will enable designers to successfully and rapidly build complete embedded systems using the industry standard ARM926EJ processor in a configurable logic fabric. The unique combination of the ARM926EJ core, the CAST PIP-AMBA and the Nextreme logic fabric enables designers to build cost-optimized custom embedded systems in a zero mask charge and no minimum order quantity.

"We're extremely pleased to be a charter partner in eASIC's eZ-IP Alliance program, and we see big benefits for our new common customers," said Hal Barbour, president of CAST. "The combination of our PIP-AMBA 'SoC kernel' with the ARM926EJ processor now provides one of the quickest, least-expensive ways to develop custom embedded systems.”

“By partnering with ARM, CAST, and other leading IP core providers, eASIC aims at helping its customers gain competitive advantage, leveraging the combined benefits of reusable cores with low-power and low-cost Structure ASICs,” commented Jasbinder Bhoot, Senior Director of Marketing at eASIC. “CAST, who has been providing high quality IP cores for cell-based ASIC and FPGA vendors for many years, understands the benefits and limitations of these technologies and can now broaden its customer reach by including Structured ASICs. We welcome CAST to our eZ-IP Alliance and we look forward to working together to answer customer needs that are currently not being addressed by those vendors.”

CAST PIP-AMBA Package

The PIP-AMBA package includes an AHB, an AHB Arbiter,  an APB Bridge,  a watchdog timer, two timers, a Scalable Interrupt Controller, two 16550 UARTs with FIFOs, General Purpose I/O (GPIO), an Internal SRAM,  an external bus interface and a SDRAM controller. It includes the multi-master and arbitration features of the high-performance AHB bus, and a bridge to the slower APB peripherals bus. The architecture makes it straightforward to add additional IP cores or custom logic to either bus.  
The PIP-AMBA includes everything required for successful implementation:

  • HDL RTL source code for the included cores 
  • Essential software, including boot code and device drivers
  • Sophisticated HDL Testbench, including external models and interfaces
  • Simulation script, vectors, expected results, and comparison utility
  • Synthesis script
  • Comprehensive user documentation, including detailed specifications and a system
    integration guide

eZ-IP Alliance

eASIC has established the eZ-IP Alliance program to form partnership with reputable semiconductor IP core providers, committed to developing highly optimized IP cores for Nextreme Structured ASICs. eZ-IP Alliance members benefit from leveraging eASIC’s unique via-based routing interconnect technology to develop Structured ASIC solutions that are typically up to 10 times lower in  power consumption than FPGAs, but require no mask charges and no minimum order quantity, unlike traditional cell-based ASICs. The FPGA, ASIC and system designers can benefit from a vast IP cores offering, proven in silicon, which will enable them to reduce design risk, significantly cut development time and cost by using pre-engineered functional modules in a configurable platform.

About eASIC

eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices and Configurable Logic IP aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology of FPGA-like programmable logic coupled with ASIC-like Via-layer customizable routing. This innovative fabric efficiently employs mask-less customization with Direct-write e-Beam, and thus allows eASIC to offer NRE-free Structured ASICs.

Founded in 1999, eASIC Corporation is privately held, headquartered in Santa Clara, California. Investors include Vinod Khosla, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, and Evergreen Partners. www.eASIC.com

About CAST, Inc.

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia. Learn more at http://www.cast-inc.com.

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

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