Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Energizes Small, Fast Systems with New Low-Power, 32-Bit Processor Cores

Compact, High-Performance Processors Ideal for Systems Needing More than an 8- or 16-Bit Microcontroller but Less than a Typical 32-Bit Microprocessor

San Jose, CA, IN-STAT SPRING PROCESSOR FORUM, May 15 2006

APS2 and APS3 cores have been discontinued. Please contact Sales to learn more.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced the immediate availability of a new line of 32-bit microprocessor cores for the embedded systems market.

The new Advanced Processing Solution (APS) family of cores is developed by CAST partner Cortus, SA, in France. More capable than an 8- or 16-bit processor but with advantages over most 32-bit processors, the new APS line is an attractive step up for the many system designers seeking more than an 8051 or 6805 but less than a typical processor from ARM® or ARC™.

“We’ve helped hundreds of designers succeed with 8051s and other controllers, and that market’s clearly continuing to grow,” said Hal Barbour, president of CAST. “But some systems just need more horsepower. Those designers have had little choice but to live with the technical and business overheads of an advanced 32-bit processor without actually using all its capabilities. Now these APS cores provide an excellent 8/16-bit upgrade solution, and we’re excited to be bringing them to existing and new CAST customers.”

The APS cores use a RISC architecture in a full 32-bit design and have features that make them both a better technical fit and a better IP experience than competing processor cores. Their advantages include:

  • Small size — APS is more compact than many 8-bit processors, requiring as few as 7,000 gates and easily fitting in many low-cost FPGAs and a wide range of ASICs.
  • High performance — APS is dramatically faster than the microcontrollers it replaces, benchmarking at 0.6 DMIPS/MHz1.
  • Low-power operation — APS operates with very little power, requiring just 18 µW/MHz1.
  • Efficient development environment — APS is designed for effective coding in C or C++, and the cores come with a complete development tool set.
  • Expanding tools and services — Third parties already supporting APS include MicroCross, Inc. — adapting their advanced development environment for APS — and SoC Solutions, Inc., IP platform experts who provide integrated cores, software, and services giving designers a head start developing APS-based systems.

The APS cores are backed by CAST’s highly-regarded support, honed over 13 years delivering and working with IP. Customers also benefit from CAST’s simple and cost-effective approach to licensing, as the company offers a flexible mix of straight usage fee or royalty-based licensing tailored to the customer’s needs.

About the APS Processor Cores

Two APS processors are shipping now, APS2 and APS3.

The APS2 core is a general-purpose processor designed for high-performance, low-power, 32-bit computing. It is optimized for small chip size for a wide variety of applications.

The APS3 core uses the same 32-bit architecture, but is optimized to achieve the most compact programming code for applications sensitive to code density. This makes APS3 especially suitable for encryption, wireless communications, and other systems requiring considerable application code, as well as for hand-held, battery-driven, and other power-critical systems. It uses instructions of 16- and 32-bit length, and interfaces efficiently with 16-bit memories.

Both APS cores are modern RISC designs with a load/store architecture. They feature out-of-order instruction completion, fully-vectored interrupts, a programmable priority interrupt controller, and support for various peripherals and memory interfaces. Their patented co-processor interface makes it easy to extend the instruction set and optimize the processor for any specific application, such as increasing the speed of a digital signal processing algorithm. Barrel shifter and multiplier co-processors are available.

From their inception, the APS processors were designed for efficient high-level programming using C and C++, and an adapted version of the GNU Compiler Project (GCC) tool set is included with the cores to facilitate this. Unusually complete, this tool set includes a graphical debugger that connects through a JTAG link or via the serial port on a PC, a comprehensive instruction set simulator (ISS), and a standard library of C routines for embedded systems. An APS version of the productivity-enhancing MicroCross development environment will also be available this quarter, through a partnership with that company.

The new cores have been rigorously verified through thousands of test cases and many different applications, and have been successfully implemented in FPGAs from vendors such as Actel and Xilinx. Results with ASIC reference designs show the cores to be highly competitive in terms of speed and area.

Processor Core ASIC Technology
(process, microns)
Approximate Area (gate equivalents) Frequency
(MHz)
APS2 TSMC 0.09
TSMC 0.13
TSMC 0.18
9,300
11,300
12,000
300
280
250
APS3 TSMC 0.09
TSMC 0.13
TSMC 0.18
13,100
16,300
16,600
300
280
220
Notes:
Results are for the core without wire load and configured with a 32-bit SRAM interface.
APS2 configured with one UART split into RX and TX modules, one timer, and one GPIO.
APS3 configured with one UART split into RX and TX modules, one timer, one multiplier, one shifter, and one GPIO.

Projects using the APS processor cores are already underway, with first silicon expected by the end of this year.

About Cortus S.A

Cortus S.A. is an innovator in high-performance, ultra-low-power 16/32 bit embedded processor cores for digital consumer, security, networking, automotive and industrial applications. Cortus' products include a complete GNU-based tool chain running on Linux, Windows XP and Unix operating systems, and a base set of peripherals at no additional cost. Along with its ecosystem partners, Cortus offers complete solutions for both FPGA and ASIC designers. The company is based in Montpellier, France with an office in Silicon Valley, CA, and can be reached at +33 4.67.13.01.90, +1 (650) 465-3855, or http://www.cortus.com.

About CAST, Inc.

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.

The area, performance, and power consumption results mentioned on the first page were achieved using the APS2 core in a minimum configuration with TSMC/Artisan 90nm ASIC technology. The power consumption figure was for the CPU only.

 

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

tw    fbk    li    li    li
Top of Page