Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses

CAN 2.0/FD controller
CAN FD Reference Design
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN Bus Master/Slave
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security

Encryption Primitives
AES, Programmable
Key Expander
Single, Triple

Hash Functions
SHA-3 (Keccak)

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).


News CAST Releases Fast, Flexible Baseline H.264/AVC Video Encoder Core

Seoul, Korea (IT-SoC and Next Generation PC Fair), November 03 2005

H2642-E has been replaced by the H264-BP-E core.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced a new IP core for versatile, high-performance video compression using the standard known as H.264 or Advanced Video Coding (AVC).

The new core implements an independent hardware encoder conforming to the ITU-T H.264 specification’s Baseline profile (level 4.1). CAST believes this to be the fastest, most capable such core available, encoding the full range of video from QCIF resolution for mobile phones (176 x 120 pixels) at 15 frames per second all the way up to the HDTV resolution needed for Blu-ray DVDs (1920 x 1080 pixels, progressive) at 30 frames per second.

“H.264 is a powerful, elegant, and extremely scalable compression standard fueling everything from personal video applications like the new video iPod® to the highest-resolution HDTV products currently planned,” said Hal Barbour, president of CAST. “The CAST H264-E core matches the capabilities of the standard, and makes Advanced Video Coding technically practical and economically feasible for whole new classes of ASIC- and FPGA-based products.”

The core is available now. Designers may choose from synthesizable HDL source code or FPGA-optimized netlist versions of the core, enabling straightforward system-on-chip (SoC) integration of H.264 for a range of product technologies and project budgets.

Participants at IT-SoC in Korea can see a live demonstration of the H264-E core at the CAST booth. The company will also demonstrate the core at the Electronics Design and Solution Fair in Yokohama, January 26-27, 2006, and demonstrate and present a technical paper on the core at DesignCon in Santa Clara, February 6-9, 2006.

About H.264 and the H264-E Core

The 2003 H.264/AVC standard grew from desire for a more flexible video compression technology that can produce good quality video at significantly lower bit rates than MPEG-2 and other methods. Also called MPEG-4 Part 10 (ISO/IEC 14496-10), the standard was written by the Joint Video Team (JVT), a collaborative effort of two international standards organizations. See for more information on the standard.

The use of H.264/AVC is growing rapidly due to its technical and business advantages. It is an extremely scalable technology—offering excellent video quality for most conceivable products—and as an international standard, companies in many industries can confidently develop H.264 consumer and business products that interoperate with each other.

The CAST H264-E core accepts a typical video stream and generates H.264-compressed video for any of the popular resolutions and frame rates supported by the standard. It conforms to the specification’s Baseline profile, level 4.1, making it most suitable for progressive scan applications such as 3-G telephony, video-conferencing, video-over-IP, and high-quality military and medical imaging systems. Highly flexible, the core can also be configured so its output can be read by Main profile decoders, common in digital television applications.

The encoder is frugal with system resources, processing video without the assistance of a microprocessor. A versatile 32-bit external memory interface makes the core independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant of the large delays and latencies typical of a shared bus architecture such as AMBA™. The interfaced memory can also operate at a different speed than the core itself, saving considerable resources. For example, for a mobile VGA device, the core might be synthesized to implement a very lean encoder running at 30 MHz, while still working smoothly with the AMBA bus at 200 MHz.

The fully featured core produces output of extremely high quality. It supports multiple slices—boosting error resiliency in noisy transmission situations—and includes a deblocking filter and macroblock skipping to improve quality at low bit rates. It can also encode video for either a variable bit rate (VBR), most useful when a lot of detail is required in a fast-changing scene such as a surveillance camera during a robbery, or a constant bit rate (CBR), most useful for bandwidth-limited applications such as mobile devices and wireless cameras.

The core’s efficiency means it requires very low operating frequencies, making H.264 encoding possible for simpler systems with less expensive processors. Transmitting NTSC CIF (352x240) at 30 frames per second (fps) requires only 12 MHz, and 1080p HDTV progressive (1920x1080) at 30 fps needs just 250 MHz

Implementation results also show the core to be very space-efficient. For example, a constant bit rate encoder for VGA (640 x 480 pixels) at 30 fps required just 120K gates and 100 Kbits of RAM in a 0.18 micron ASIC process. In FPGA terms, the core can generally support 4CIF (704 x 480 pixels @ 30 fps) in the slowest offerings and HDTV 720p (1280 x 720 pixels @ 30fps) in the faster offerings from Altera and Xilinx.

See for additional results and complete information.

The CAST H264-E core was developed by image compression experts and long-time CAST partners Ocean Logic Pty Ltd. (

About CAST Incorporated

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.


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