Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Enables European FPGA Designers with Low-Volume IP Pricing Program

Makes high-quality, ASIC-proven IP cores affordable for prototypes, limited-production runs, and entry-level IP users

(DATE) Paris, France, February 17 2004

Semiconductor intellectual property (IP) provider CAST, Inc. today announced a European program aimed at making it easier for FPGA designers to benefit from the high-quality IP cores typically used for ASIC designs.

The new program, FPGAenable, introduces special pricing for the low-volume production runs typically associated with FPGA-based products – a dominant sector in the European electronics market. Pricing for these low-volume licenses varies by core, but the result is the ability to design-in IP cores at a cost of just few Euros per manufactured unit. This highly competitive pricing enables designers to gain all the advantages of IP-based design for a cost equivalent to using a standard part in a discrete chip – without sacrificing IP quality, implementation independence or comprehensive support. In addition, the FPGAenable program includes the availability of fully-functioning evaluation code, enabling users to rapidly validate IP functions within their overall design prior to finalizing their purchasing decisions.

Why a Low-Volume Program?

CAST already provides both soft cores (HDL source) for ASICs and firm cores (optimized netlists) for FPGAs. A significant majority of the company’s licenses has been for ASICs. Today, however, FPGA design starts are 20 times more frequent than ASICs, as manufacturers move to exploit the potential of new FPGA technologies and respond to an increasingly differentiated product marketplace. Using high-quality third-party IP cores has been prohibitively expensive for most applications with low run-rate utilization, and now CAST’s FPGAenable program eliminates this barrier.

Chris Sheldon, vice president of European operations puts this in perspective. “In Europe, many users choose an FPGA solution to avoid the high non-recurring engineering (NRE) costs associated with evolving an ASIC. They are not sure of the volume opportunity and also want to maintain the flexibility to revamp or optimize their design quickly and at low cost as the project progresses. FPGA solutions fit this model well, but IP from focused vendors, such as CAST, that can support FPGA or any other implementation technology, is perceived to be too expensive or too high an up-front cost.”

This CAST program enables the growing European FPGA sector to buy into IP technology with zero sacrifice in quality, testbench software and first-line support. It eliminates the entry barrier so that users can license IP at an affordable entry-level cost for a limited volume of parts, at a rate that is market-comparable to implementing a standard part in a chip. With flexibility in mind, designers can easily migrate to higher unit rates through an unlimited volume license or indeed an upgrade to a full ASIC license, if appropriate.

A History of IP Market Building

The new FPGAenable program continues CAST’s record as an innovator in the use of IP cores. Rare in the industry, CAST has been successfully delivering IP products for ten years, first simulation models and then IP cores as design needs evolved. The company has well over 200 customers worldwide, and despite market slowdown has increased its revenue from IP cores by 50% in each of the past two years. With the increase in IP-based design in Europe, CAST established a dedicated European office in 2002, and has since seen European revenues grow steadily from 10% to 19% of the company’s worldwide sales. Sheldon commented, “CAST’s positive performance is based on us delivering high quality cores for both ASIC and FPGA implementations. Our excellent technical support services give users direct access to the original developers for all cores supplied which is a key factor for our customers.”

About CAST, Inc.

CAST provides general purpose IP (gpIP), offering nearly 100 different popular and standards-based cores including processors, interfaces, and application-specific functions for multimedia and encryption. ASIC, FPGA, and System-on-Chip (SoC) designers use these cores to significantly shorten their development time and reduce their overall costs.

The company has about 200 customers developing products in nearly every applications area. Privately owned and operating since 1993 with a focus on making IP practical and affordable, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, has a European office in the UK, and works with an international network of IP developers and distributors.

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

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