Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Releases MPEG-4 and JPEG 2000 IP Cores

Fast, small, flexible cores facilitate use of advanced standards for high-quality video and image processing applications

Santa Clara, California, January 27 2003

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

The core (MPEG-4), renamed MPEG4-E, and the core JPEG2K_D have been discontinued. Please contact Sales to learn more.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced the addition of new MPEG-4 video encoding and JPEG 2000 image decoding cores to its line of general purpose IP (gpIP) for electronic design.

The CAST MPEG-4 core offers vastly greater performance than software-based solutions, and provides broader features and capabilities than other MPEG-4 cores. It is small and fast — easily handling real-time encoding of full-screen video in under 50,000 ASIC gates — and has the flexibility to support a range of applications from high-quality video conferencing to remote streaming of DVD-quality movies.

The CAST JPEG2K_D core provides complete hardware acceleration of the new JPEG 2000 image processing standard. It decompresses images at competitive rates, decoding a 5 megapixel camera image in half a second, or standard definition TV (720 x 480 pixels) at 30 frames per second. The core is also quite flexible, with implementation options and programmability features that make it easy to tailor its processing abilities, size, and power consumption to specific devices, applications, and systems.

Available immediately for synthesis to ASICs or optimized for various FPGAs, the new cores join CAST’s substantial library of multimedia IP. This includes complete solutions such as JPEG 2000 encoding as well as individual multimedia subsystem cores for motion processing and estimation, discrete cosine (DCT) and waveform (DWT) transformations, color space conversion, and Huffman processing. Designers should see the web site for full information (www.cast-inc.com).

About the CAST MPEG-4 Core

The MPEG-4 standard was designed to provide scalable, high-quality video on a variety of display devices and over any transmission technologies. The CAST MPEG-4 core provides the best available implementation of this philosophy, offering greater capabilities, higher performance, and competitive implementation efficiencies compared with other cores.

The ISO/IEC 14496 MPEG-4 Standard defines ranges of capabilities categorized into profiles and levels. The MPEG-4 cores from other vendors are primarily targeted at mobile video applications; they provide the lowest class of support — MPEG Simple Profile Levels 0 to 3 — which allows for images up to 352 pixels by 288 lines at 30 frames per second. The CAST MPEG-4 core supports these low resolutions and more, satisfying MPEG Advanced Simple Profile Levels 0 to 5 and handling as large as 704 x 576 at the same 30 fps rate. This higher degree of MPEG-4 support also enables more sophisticated video features, and makes it possible to gain MPEG-4 advantages for applications like digital video recorders or remote camera systems where larger, high-quality video streams are required.

Moreover, the CAST MPEG-4 core yields a very efficient hardware implementation, requiring fewer than 40,000 gates in a reference ASIC or fitting in smaller FPGAs (plus memory; see table). It also operates efficiently, requiring a clock rate of just eight times the raw pixel rate. This means the operating rate needed for videoconferencing (176 x 144 screen at 15 fps) is just 3 Mhz, and for VGA video (640 x 480 at 30 fps) just 74 Mhz.

Technology

Approx. Area

Frequency

Video Throughput

ASIC0.18µ process

39K gates and25 Kbits RAM

~ 100 Mhz

> 704 x 576 (4CIF) framesat 30 fps

XilinxVirtex II

3,600 slices and10 Multipliers and 16 RAM blocks

> 70 Mhz

640 x 480 framesat 28 fps

The CAST MPEG-4 is ready for integration in an SoC or board. It works with any microprocessor, which need only supervise the encoding process and perform ancillary tasks such as bit rate control. The core also requires external memory for a frame buffer; a single 16 or 64 Mbit SDRAM with a 16-bit wide data bus is sufficient.

The MPEG-4 core was developed by CAST partner Ocean Logic, based in Australia (see www.ocean-logic.com).

About the JPEG 2000 Decoder Core

Compared with today’s popular JPEG standard, the ISO/IEC 15444-1 JPEG 2000 Image Coding System standard provides more efficient compression, better image quality, and greatly improved error resilience and transmission noise tolerance (see www.jpeg.org).

The JPEG2K_D core’s hardware support for this standard makes it a good choice for many state-of-the-art image processing applications. Designed for easy integration with a host processor and having modest external memory requirements, the core offers competitive speed and area characteristics, as seen here for an ASIC reference design.

Technology

Approx. Area

Frequency

ASIC0.18µ process 100K gates

100K gates

150 Mhz

Designers can tune the core’s architecture during synthesis, supporting larger or smaller image processing sizes or controlling power/speed trade-off factors such as 2D-DWT filter types (5/3 or 9/7 or both) or the number of Entropy Encoding Units. Programmable settings such as the size and pixel depth of input images, number of 2D-DWT levels, or the code block size (32x32 or 64x64) provide additional control over the core, helping designers reach the optimum balance between image quality, processing time, and power consumption for their specific systems.

The JPEG2K_D core was developed by CAST partner Alma Technologies S.A., based in Greece (see www.alma-tech.com).

About CAST, Inc.

CAST provides general purpose IP (gpIP), a broad range of popular and standards-based cores that includes processors, interfaces, and application-specific functions for multimedia and encryption. Designers use these cores so they can concentrate on the more unique, creative aspects of their system designs, or to quickly incorporate technology beyond their normal expertise.
Privately owned and operating since 1993 with a focus on making IP practical and affordable, the company has established a reputation for high-quality products, simple licensing, and responsive technical support. CAST is located near New York City, and works with an international network of IP developers and distributors.

CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.

 

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