Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

Recent news summary page

Download this release (PDF).

News CAST Launches Multimedia Line with IP Cores for Image or Video Compression

Flexible Discrete Wavelet and Cosine Transform cores from multimedia experts Alma Technologies ready for JPEG or MPEG applications

Electronic Design Automation and Test Expo, Hsinchu, Taiwan, October 03 2001

This product is no longer available to license from CAST. Please contact CAST Sales for more info.

dct, dct-fi, rc_2ddwt and 97fg have been discontinued. Please contact Sales to learn more.

Semiconductor intellectual property (IP) provider CAST, Inc. today announced its expansion into multimedia applications with the introduction of cores for image/video compression from new development partner Alma Technologies.

The new cores implement the popular discrete cosine transform (DCT) and emerging discrete wavelet transform (DWT) algorithms. Available now, they mark the beginning of a series of multimedia-related cores CAST expects to release over the next several months, culminating with a complete JPEG2000 core in mid-2002.

Multimedia Goes Mainstream

For years CAST has focused on building a broad line of general-purpose IP cores, featuring 8- and 16-bit processors, related peripherals and functions, and standard communications buses, all designed to meet the needs of mainstream electronics designers.

With the spread of Internet-based communication and wireless telephony, even mainstream designers need to employ compression algorithms and other functions previously used by multimedia specialists. The new cores make this expertise available in affordable, well-supported, reusable modules. With rigorously-defined interfaces and proven code, designers can integrate CAST multimedia cores with considerably less time and effort and greater reliability than they are likely to achieve implementing these functions themselves.

New Image/Video Compression Cores

The new cores implement standard algorithms for image and video compression. The Discrete Cosine Transform algorithm has been popular for some time, while the more sophisticated Discrete Wavelet Transform is a newer approach that produces superior compression results. Each core is especially flexible — processing data in both directions with a choice of filter sizes — making them more general purpose than those typically offered by other IP vendors.

The RC_2DDWT Discrete Wavelet Transform core implements the 2D Forward and Inverse Discrete Wavelet Transform (2D-DWT) using the lifting-based 5/3 and 9/7 filters. Hence, it is appropriate for wavelet-based image or video CODECS, and can be used as an IP core for products incorporating the JPEG2000 or MPEG4 standards. It is based on the row-column computational architecture. The company believes that is the only commercially-available core that implements both Forward and Inverse 2D-DWT.

Not an IP core itself, the 97FG is a VHDL code generator that produces optimized and synthesizable descriptions — cores — implementing the 9/7 Discrete Wavelet Transform's filter banks. The binary executable receives as inputs: i) the type of filter (forward or inverse), ii) the input bit-width, iii) a set of filter coefficients, and iv) the number of pipeline stages. It then generates the corresponding VHDL code for the specified 9/7 filtering unit, which can serve as an IP core for implementing DWT-based image and coding systems.

The DCT-FI core performs both the inverse and forward Discrete Cosine Transform (DCT) using either 8x8 or 16x16 pixel block samples. It is carefully designed to offer high performance while maintaining a low gate count — running, for example, at 70MHz on a Xilinx Virtex-6 FPGA — and it is ready for use in many multimedia, digital video and digital printing applications. Based on the row-column computational architecture, the DCT_FI core enables products performing compression/decompression with the JPEG, MPEG1, MPEG2, MPEG4, H.261, H.263 industry standards.

The new CAST multimedia cores are available today in VHDL for synthesis to ASICS or optimized for implementation with programmable devices from Altera and Xilinx. Custom core modifications, Verilog versions, or other options are also available.

About Alma Technologies

Based in Athens, Greece, Alma Technologies is a new, privately owned electronic design firm focused on multimedia, cryptography, and telecommunication digital signal processing. Rich in technological expertise — the six founding engineers include 3 PhD and 3 MSc holders —the company develops IP cores for resale through CAST and provides VLSI design services to a variety of companies.

Alma Technologies
Marathonos Av.2, Pikermi, Attika, GR 19005 Greece
Tel: +30 1 6039850            info@alma-tech.com
Fax: +30 1 6039850            www.alma-tech.com

About CAST, Inc.

CAST provides a broad line of practical, affordable, general-purpose IP cores that features 8- and 16-bit processors, peripherals, buses, communications devices, and special functions like encryption. Operating since 1993 with a focus on making IP practical and affordable for mainstream designers, the company has established a reputation for high-quality products, flexible licensing, and responsive technical support. The company is located near New York City, and works with an international network of IP developers and distributors.

CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.

 

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