Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

News CAST and FS2 Partner to Provide Advanced Debug Capabilities for SoC Designs

New Debugging Option Now Available for 8051-Compatible Embedded Processor Cores

DesignCon, Santa Clara, California, January 30 2001

CAST, Inc. and First Silicon Solutions, Inc. (FS2) today announced a joint effort to make embedded processor cores easier to debug. The resulting option adds FS2’s instrumentation intellectual property (IP) and interface to CAST’s IP cores, making them accessible and controllable even when buried within complex system-on-chip (SoC) designs. This greatly facilitates system software development, pre-silicon hardware simulation, and first-silicon debug and validation.

The new option is available immediately for the CAST R80515 microcontroller core, and is already in use in the field. The option is also available upon request for other processors in CAST’s 8051-compatible family. Pricing varies, but typically starts at about 15% of the standard core cost.

Advanced Features Solve Many Difficult SOC Design Issues

Reaching the control and data pins of an embedded processor from outside the chip is often impossible with complex SoCs. This makes it difficult or expensive to apply conventional debugging tools such as logic analyzers or in-circuit emulators.

FS2’s technology overcomes this challenge by making internal cores directly accessible from outside the physical chip. It adds a special On-Chip Instrumentation (OCI™) debug logic block to the synthesizable processor core. A high-performance hardware-assisted debugger is connected to the target system containing the SoC core with a standard JTAG connector. The debugger "box" manages communications between the OCI debug block in the silicon and the Windows® PC development system. Designers control the OCI block and embedded processor through source-level debug software running on the Windows PC.

The OCI block’s robust features include run control, memory and register visibility, software and hardware breakpoints, complex breakpoints, and a sophisticated trace history. It doesn’t impact the system’s logic, and can operate at real-time processor speeds. The OCI is economical in its use of chip area and its extensions are scalable: designers can trade off extra debugging power against extra gate usage during synthesis. The technology can also be extended to support multi-core debug, software performance analysis, and network protocol analysis.

About First Silicon Solutions

First Silicon Solutions is a privately held company focused on providing IP and tools for the testing and debugging of SoC hardware and software. FS2 products help silicon vendors and their customers develop and more effectively market their products, reducing their development cycles, and allowing them to focus on delivering all the potential of the system on silicon. For more information on FS2, call (503) 331-2575 or visit the web site http://www.fs2.com.

About CAST, Inc.

CAST provides practical, affordable IP products and services for designers of 8- and 16-bit microprocessor-based systems. Operating since 1994, the company has a reputation for quality products and responsive, comprehensive support. The company is located near New York City, and works with an international network of IP developers and distributors.

CAST is a trademark of CAST, Inc.
OCI is a trademark of First Silicon Solutions, Inc.
All other trademarks are the property of their respective owners.

 

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