Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

by CAST, Inc.

Related Links

News Third-Party Developers Deliver First Cores for Xilinx Virtex FPGAs

SAN JOSE, California, February 22 1999

C2901, c8259A, and C2910A have been discontinued. Please contact Sales to learn more.

Xilinx, Inc., (NASDAQ:XLNX), today announced the availability of the first wave of third-party software cores that support the new Virtex family of FPGAs. The cores are available now from partners in the Xilinx AllianceCORE program and include predefined networking, communications, encryption and microprocessor peripheral functions.

"The Virtex family is enjoying tremendous market acceptance," said Dennis Segers, vice president of FPGA development and general manager of the High End FPGA Business Unit at Xilinx. "For the first time, customers have access to FPGAs with system-level features and up to one million system gates. This is fueling the demand for cores, which play a critical part in the success of large designs. Our AllianceCORE partners recognize this opportunity, and they are choosing the Virtex family as the primary platform for developing new intellectual property."

AllianceCORE partners report that cores previously designed for Xilinx XC4000 FPGA devices operate 25-30 percent faster when converted to run on Virtex devices. All of the new Virtex FPGA cores have been certified to ensure that they work within the Xilinx software design flow.

"The Virtex family features a revolutionary FPGA architecture that is unmatched in the industry," said Timothy Smith, managing director of Memec Design Services. "It allows us to consider the development of FPGA cores that were not possible before."

"The results we are seeing on Virtex FPGAs exceed our expectations," said James Doherty, CEO of Integrated Silicon Systems (ISS). "Our first run of the ISS-designed DVB Reed-Solomon cores in Virtex devices resulted in an immediate performance improvement of about 28 percent. We expect to see even greater gains in performance by better leveraging some of the system-level features available in Virtex FPGAs."

The new cores for Virtex FPGAs available now from AllianceCORE partners include:

CAST, Inc. of Pomona, New York, is supplying the C2910A micro-program Controller, the C2901 bit-slice unit, the C_UART compact universal asynchronous receiver-transmitter (UART), and the C8259A programmable interrupt controller. New from CAST is the X-DES cryptoprocessor core.

CoreEl MicroSystems of Fremont, California, is supplying a new UTOPIA slave interface and a 10/100 Ethernet media access controller (MAC) core.

Integrated Silicon Systems of Belfast, Northern Ireland, is supplying Reed Solomon encoder and decoder cores.

Memec Design Services of Mesa, Arizona, is supplying a Reed Solomon encoder core, and new IIC master and slave interface and Reed Solomon decoder cores.

Virtual IP Group of Santa Clara, California, is supplying the M8254 timer/counter and M8255 programmable peripheral interface cores.

About Virtex

The Virtex family comprises nine devices that range in density from 50,000 to one million system gates and provide chip-to-chip performance of 200 MHz. The Virtex family features four, fully digital, delay locked loops for internal and external clock synchronization, a hierarchy of memory access, and SelectI/O technology for simultaneous interface to multiple voltage and signal standards.

Combined with the Alliance Series and Foundation Series design software, Virtex FPGAs offer unprecedented system level integration capabilities.

"The Virtex architecture is a natural for implementing IP," said Newton Abdalla, president of CAST, Inc. "The capabilities it provides to support system-on-a-FPGA design dramatically extend the boundaries of FPGA functionality."

Virtex Improves Core Performance

The Virtex family was developed to address system-level design on an FPGA. As a result, the combination of the device architecture and development software greatly simplify the process of designing and using cores. Third-party core providers experience improved performance with less need to optimize for the FPGA architecture.

All cores are available for purchase today directly from the AllianceCORE partners in either Xilinx optimized netlist or source code formats. Pricing is available directly from AllianceCORE partners. Datasheets for each core can be found on the Xilinx web site.

Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and commands more than half of the word market for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.

Xilinx is a registered trademark, and all XC-prefix product designations, Alliance, AllianceCORE, Foundation, Select I/O and Virtex are trademarks of Xilinx, Inc. Other brands or product names are trademarks or registered trademarks of their respective owners.

 

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