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SOCK-ARC SoC Kernel for ARC with AMBA Bus Systems

On this page: Description | Features | Applications | Block Diagram | Functional Description | IP Cores | Software | Support | Verification | Deliverables

The SOCK-ARC provides the essential IP cores and infrastructure software needed for systems using a microprocessor from the ARC 600 or 700 families with the AMBA bus, a de facto open standard. Ready for software development out of the box but also easy to customize and extend, it serves as a basic platform for the rapid development of a variety of system-on-chip (SOC) applications.

The platform is well suited to a variety of AMBA-based SoC designs. It includes the multi-master and arbitration features of the high-performance AHB bus, and a bridge to the slower APB peripherals bus. The architecture makes it straightforward to add additional IP cores or custom logic to either bus.

The platform includes synthesizable HDL cores for the AHB and APB buses, plus various timers, controllers, interface functions, communications functions, and an internal SRAM block. (FPGA netlist versions are also available.) The individual cores are also available separately.

Generous standard deliverables include Software device drivers, boot code, service routines, and support for an embedded real-time operating system (RTOS). The included SOC test and validation suite features an AMBA Bus Functional Model.

Features

• Integrated IP cores and software subsystem provides basic infrastructure for many SoC applications
• Platform saves significant time over acquiring and integrating separate element
• Works with 32-bit ARC 600 or 700 family processors
• Built on AMBA standard bus for broad applicability
• Enables both the high-performance AHB and the APB peripherals buses
• Easily add custom logic or additional IP cores to tailor or expand the system
• Immediately begin software development and test
• Supports ARC MetaWare® and other development tools
• Complete infrastructure includes essential hardware and software
• Included IP cores (also available separately)
• Microprocessor interface
• APB Bridge
• Timers
• Scalable Interrupt Controller
• Parallel I/O
• Internal SRAM with Controller
• Software
• boot code
• Interrupt Service (ISR) code
• Main code with Scheduler
• Device driver code
• Hardware Level API
• Plug-in architecture for user-defined custom IP blocks
• Support for real-time operating systems (RTOS)
• Comprehensive SOC test and validation suite, including:
• AMBA Bus Functional Model with support for interrupts and subroutines
• Sophisticated HDL Testbench with external models and interfaces
• System Level Simulation scripts, C-test/Macro test code and comparison utilities
• Complete user documentation

Applications

Provides a system development head start for a wide range of applications, from low-power, portable, or inexpensive 600-based products through more sophisticated, high-performance products using a 700 family processor.

Block Diagram

Functional Description

The SOCK-ARC is a completely integrated and tested platform, including the bus system, memory system, and peripherals. It includes two AMBA-standard buses: AHB for high-speed transactions such as local memory access or DMA operations, and APB for slower transactions with peripherals such as UARTS and the GPIO. Users can readily add their own custom logic or other IP cores. The included cores and software are as follows.

IP Cores

The following cores are pre-integrated (each is also available separately).

Microprocessor Interface

Communicates between the AHB bus within the platform and the Microprocessor bus.

Address Decoder – Memory Map

The Memory Map is easily configurable using HDL Header Files. The Address Decoder supports AMBA decoding on the AHB and APB buses.

Interrupt Controller

Manages processor attention requests for the RTOS. Fully scalable to support from one to 32 interrupt sources, and provides a programmable register used when generating an interrupt under software control.

APB Bridge

Serves as an interface between the AHB and APB buses, and is a slave to the AHB. Transactions targeted at slow peripherals on the APB are initiated on the AHB, translated to APB bus cycles, and returned to the AHB via handshaking signals.

Timers

The 16-bit counter/timers are necessary for any RTOS needing a timebase and scheduling. They are fully programmable and include selectable prescale values of 1, 16. and 256. Two modes of operation provide a free running value and also periodic interrupts.

Parallel IO

Configurable, Parallel I/O module with a scalable set of up to 32 I/O lines. Each line can be configured independently of the others, with any combination of inputs or outputs.

SRAM Controller and SRAM

The Internal SRAM Controller provides a method of communicating with an integrated Synchronous Static Random Access Memory (SSRAM). The memory interface allows word, half-word, or byte wide addressing.

Software

Boot Code

Main program setup and entry; low level interrupt handling and setup; memory allocation; stack setup, reset, exception entry vector functions are included in the Boot Code.

Interrupt Service Routines (ISR)

Save and Return pointers to and from Interrupt stack and Interrupt Service Routine entry and exit C-Code functions.

Main Routine with optional Task Scheduler

“Main Function” C-Code includes entry from Boot Code initialization along with an optional timer based priority encoder and task multiplexor.

Peripheral Driver Code

Peripheral Driver Code includes drivers for the Interrupt Controller, Timer, Parallel IO and Memory Controller.

Hardware Level API

The Hardware Level API is easy to understand MACROs that make calls to hardware memory or registers, enabling ease of coding and verification in Simulation and Prototype Emulation environments.

Support

The platform as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The platform has been verified through extensive simulation and rigorous code coverage measurements, and is in use for several customer applications. SoC development kits are available.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code for the included cores (post-synthesis EDIF netlists for FPGAs are also available)
• Essential software, including boot code and device drivers
• An AMBA Bus Functional Model and sophisticated HDL and C-Code Testbench, including external models and interfaces
• System Level Simulation scripts, C-test/Macro test code and comparison utilities.
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Features | Applications | Block Diagram | Functional Description | IP Cores | Software | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC

 This core developed by the ARM experts at SoC Solutions LLC.