Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Low-power and low-latency HDR/WDR image processor produces clear and sharp images under
any lighting conditions.

Versatile and Efficient

  • Content Adaptive Frame Merge
    • Merges 2, 3 or 4 exposures
    • Programmable exposure times and speed of response to content changes
  • Advanced Tone Mapping
    • Local & Global Tone mapping
    • Programmable contribution of local versus global tone mapping
  • 2D Noise Reduction Filter and Contrast Expansion of Programmable Strength
  • White Balancing Adjustment and Optical Black Correction

Low Latency & Low Power

  • No frame buffers; does not need power-consuming DDR
  • Just seven lines of latency

Sensor-Agnostic and
Tunable to Application Requirements

  • User control over processing parameters allows tuning to specific application needs
  • 2, 3 or 4 input exposures
  • 10- or 12-bit per sample Raster-Scan Bayer RGB Input

Proven & Reliable

  • Mass production proven
  • Scan-ready, LINT-clean design

Deliverables

  • Verilog RTL or targeted netlist
  • Comprehensive documentation
  • Testbench
  • Bit-Accurate C Model
  • Sample synthesis and simulation scripts

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

General Product Brief

Related Products

Background Articles

WDR Low-Power, Low-Latency HDR/WDR Image Processor

The WDR core implements an efficient, flexible, low-power and low-latency High Dynamic Range (HDR) and Wide Dynamic Range (WDR) image processor that produces clear and sharp images under any lighting conditions.

The core receives two, three, or four exposures of the same frame, in 10- or 12-bit RGB Bayer format and any resolution up to Full-HD. It processes the input with proprietary, content-adaptive algorithms for merging exposures, tone mapping (local and global), and contrast expansion, and it also supports white-balance adjustment, optical back correction, and a 2D reduction noise filter.

Being highly configurable and sensor-agnostic, the core can address the needs of a wide range of applications. Run-time control over processing parameters enables users to adjust brightness, dynamic range width, and sharpness to address the requirements of different use cases, and also provides the means to eliminate typical HDR/WDR processing artifacts such as flickering, shape deformation, and over-enhanced edges.

The WDR core requires only a few lines of buffering and adds minimal processing latency. It features extremely low power consumption due to the absence of a power-consuming frame buffer, which is typically implemented in external DDR memory.

The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and mass production. Its deliverables include a complete verification environment and a bit-accurate software model.

Applications

The core’s efficiency makes it suitable for a wide range of applications using image sensors. Its low-latency processing makes it ideal for systems involving real-time human or machine interaction with the video content, such as those in automotive, industrial, medical, and several types of surveillance applications. 

Block Diagram

WDR  Low-Power, Low-Latency HDR/WDR Image Processor Block Diagram

Size and Performance

The following table shows silicon resources utilization and performance information for different technology targets, with the core configured to support Full-HD resolution. These figures do not represent the smallest area or higher processing rate that may be achieved. Please contact CAST to get area and performance characterization information for your specific requirements.

Target Technology

Silicon Resources

Performance

TSMC 28nm (hpm-sc9-svt-c31) 560K Gates and 980K bit of SRAMs 1080p120
Xilinx® Artix®-7, Kintex®-7, Kintex® Ultrascale™ 40K LUTs, 43 Block RAM Tiles, 91 DSPs 1080p60 on Kintex UltraScale
1080p30 on Artix-7 and Kintex-7
ntel® Arria® 10, Stratix® V 30K ALMs, 80 RAM Blocks, 91 DSP Blocks 1080p60 on Stratix V
108p30 on Arria 10

 

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