Video Deinterlacer IP Core VDINT-MAMotion-Adaptive Deinterlacer Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables | FPGA Development & Evaluation Platform

Implements a high-quality, motion adaptive video deinterlacer that converts interlaced video signals (such as 1080i HD or analog TV) into progressive (non-interlaced) form.

The deinterlacer core is capable of SD (480i) and HD (1080i) deinterlacing using both 8-bits and 10-bits per color. It offers fast and accurate Film Mode detection—also called Inverse Telecine or 3:2 Pulldown—for reconstructing original 24 fps material.

The core is designed to provide best-in-class image processing. An advanced motion estimation engine provides multiple levels of detection allowing for more accurate results. The motion probability vectors are passed to a data adaptive interpolation engine, which analyzes the underlying image information and performs processing to preserve and enhance image details

The deinterlacer core is available for ASICs or FPGAs, and includes a complete ‘C’ reference driver and fully documented API. The core has been customer-proven, and is available in an optional FPGA-based reference system that provides a complete development environment for evaluation and early software development.

See representative implementation results (each in a new pop-up window):

Features

High-Quality, High-Detail Video Deinterlacing

• Real time, motion adaptive deinterlacer
• Advanced, multiple-level motion estimation engine
• Uses four fields for accurate motion estimation
• Stores derived motion codes in memory
• Data adaptive image reconstruction
• Uses edge angles for direct motion interpolation
• Content adaptive processing
• Fast, accurate Film Mode detection
• Recovers original 24 fps film from interlaced fields
• Locks in less than six field times
• Holds lock during bad edits and scene cuts
• Supports 480i and 1080i input sources
• Supports 8 bits and 10 bits per color

Excellent Performance

• Low clock rate; for 60Hz deinterlacing:
• 50 MHz SD (480i)
• 135 MHz HD (1080i)
• Low latency, five field delay
• Requires storage of only four fields in external memory

Easy SoC Integration

• Low CPU overhead
• Fully synchronous soft core
• AMBA 2.0 APB Slave Interface

Reference Software

• Sample driver and video player application
• C source code provided
• Fully documented API

FPGA Development & Evaluation Platform

• Integrated 32-bit microprocessor
• Video input for real time testing
• Includes the VDINT-MA Deinterlacer, DDR-2 interface, and DVI digital display controller

Applications

• Surveillance
• Professional and broadcast video
• Consumer electronics: set-top boxes, LCD displays, digital video cameras
• Military imaging

Block Diagram

 

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

Verification testing has been performed using a bottom-to-top methodology. Testing is first performed at the module level and progresses up to the system level.

Module-level testing for this core consists of generating both randomized and corner case (boundary value) conditions across a wide variety of resolutions.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• C source code, C Reference Driver,C Reference video player application
• Sophisticated HDL Testbench including a sample driver and a real time video player application
• Simulation script, vectors, expected results, timing constraints, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, and functional specification.

FPGA Development & Evaluation Platform

The FPGA Development & Evaluation Platform available with this core implemented in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables | FPGA Development & Evaluation Platform

Download PDF datasheets for more info: ASIC | Altera | Xilinx