MPEG2 IP Core MPEG2-TS-D MPEG2 Transport Stream Decoder Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

Implements a decoder or demutliplexer for MPEG-2 audio, video, and data transport streams (ISO/IEC 13818-1).

A transport stream (TS) as received by a tuner includes packets—carrying fragments of Packetized Elementary Streams (PES) for audio, video or data from multiple programs—and Program Specific Information (PSI). The type of each packet is identified by its Packet ID (PID). The core accepts Transport Stream packets from the front-end (tuner), and performs packet synchronization, PID and section filtering, and elementary streams distribution, and it also enables clock recovery.

The decoder core uses up to 32 programmable PID filters to select and demultiplex the desired streams, and it supports DVB descrambling and 3DES decryption of source streams. The core also performs section filtering based on 32 12-byte filters. The processed data and multimedia streams are distributed to the system memory for further processing by the host or the respective decoders.

The core accepts the Transport Stream via a dedicated interface that can operate in either bit-serial or 8-bit-parallel mode. The host processor accesses the control and status registers of the core via an AMBA/AHB slave interface, and the core access up to 256 MBytes of system memory via an AMBA/AHB master interface. A dedicated port broadcasts the Program Clock Reference (PCR) value, for direct use of the clock recovery hardware.

The core is designed for reuse and reliability, and has been production proven. A complete ‘C’ reference driver and fully documented API facilitate system integration. An optional FPGA-based reference system using the core provides a complete development environment for evaluation and early software development.

Implementation Results

The MPEG2-TS-D core was developed using best-in-class design principles and is very efficient in resource usage. The core synthesizes to about 30k gates and 3K bits of memory. Please contact CAST for detailed area and timing results for any specific technology you require.

Features

Key Features

• ISO/IEC 13818-1 MPEG-2 Transport Stream compliant
• Supports DVB, ATSC and ARIB
• 1-bit serial or 8-bit parallel interface
• 188 to 224 bytes per TS packet
• Adaptation filed processing
• Up to 100MBps input rate

Powerful PID filtering

• 32 PID filters
• PSI and PES filtering
• 32 section filters with 12 byte filter length
• Stream recording capability 

Built-in Decryption

• DVB descrambling
• DES and 3DES with ECB, CBC,  CTS mode, with programmable decryption key

Ease of Integration

• AHB/AMBA interfaces and embedded DMA
• 256 Mbytes addressable memory
• Programmable filters, PID mapping tables, and buffer offsets in system memory
• Flexible/programmable interrupt interface
• Sample driver and fully documented API

FPGA Development & Evaluation Platform

• 32-bit MCU based system
  
• Real time video input
  
• Includes the MPEG2-TS-D transport stream decoder, DDR-2 system, and display controller
  
• DVI digital output

Applications

• Satellite TV/IPTV/Cable Set-top-box            
• Blu-ray DVD players                                           
• Video capable portable devices                     
• Surveillance systems
• Video conferencing
• Data Broadcasting

Block Diagram

Functional Description

The core consists of several function blocks as shown in the diagram and briefly described here.

Capture

Provides data capture and clock resynchronization.

PID Filter

Uses enable signals to pass transport data to the hardware decoders and the memory interface as specified in the control registers.

Table Decode

Handles the major table types for MPEG-2 transport streams:   PMT, PAT, CAT, TSDT, and NIT.

AHB Interface

Asynchronous clock domain for control register programming and status register reporting. Includes a single interrupt to the system.

PES0 – PES3

Maintains a separate base address for each PES to decode.  Each additional PES not explicitly decoded here is stored in a circular buffer.

TDES

Implements triple DES with CBC for PES-level encryption algorithms.

Memory Buffer Source MUX

Address and data pass through this multiplexer to provide a single interface to the transport memory interface.

FPGA Development & Evaluation Platform

An available Development & Evaluation Platform implements this core in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

Using the integrated Compact Flash system, bit streams may be loaded into memory and decoded using either customer developed software or the included transport stream player.  The video output system makes use of the on-board DVI interface and requires no additional daughter cards.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The MPEG2-TS-D has been rigorously verified using random and directed testing covering. The core has been silicon and production proven.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Reference driver, API and video player application in C
• Sophisticated HDL Testbench
• Simulation script, vectors, expected results, and timing constraints simulation summary
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, and functional specification.

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

Download PDF datasheet: ASIC