MPEG2 IP Core MPEG2-D MPEG2 MP@HL Decoder Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

Implements a hardware video decoder capable of decoding Main Profile @ High Level bit streams. The core is able to support all formats provisioned by the High Level, including HD - 720p and Full-HD - 1080i resolutions, frame rates up to 60 Hz, and compressed bit rates up to 80Mbits per second. Supporting both 4:2:2 and 4:2:0 chroma formats, the MPEG2-D offers partial support of High Profile of the standard.

The video decoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. A number of options for the input of the compressed stream allows for easy integration in most typical SoC environments: The compressed elementary streams can be either directly read from a memory or can be input to the core via a dedicated streaming-capable interface. The decompressed stream is output vie the memory interface. The AMBA® AHB interface is also used to provide the host real-time control and status access. The memory interface that can be used for reading the incoming compressed stream or just for storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture. Transport stream decoding, when required, is performed by the MPEG2-TS-D core also available through CAST.

The core is designed for reuse and reliability, and has been validated for standard conformance and is multiple times production proven in high volume consumer devices. A complete ‘C’ reference driver and fully documented API facilitate system integration. An optional FPGA-based reference system using the core provides a complete development environment for evaluation and early software development

Implementation Results

The MPEG2-D core was developed using best-in-class design principles and is very efficient in resource usage and clock rates. The core synthesizes to about 200k gates and 75 Kbits of memory, and can decode Full-HD 4:2:2 1080p/60 streams using a clock as low as 135MHz. Please contact CAST for detailed area and timing results for any specific technology you require.

Features

Video Decoding Features

• Main Profile @ High Level (MP@HL)
• Intra (I) and Inter (P, B) frames
• 4:2:0 and 4:2:2 chroma formats
• Progressive and interlaced video
• Up to Full-HD resolutions
• Frame-rate up to 60 fps
• High quality / bit-rate up to 80 Mbps
• Robust error resiliency features for high quality decode

Easy SoC Integration

• Processor-independent, stand-alone operation
• Independent of external memory type: can use DDR2/3. SDRAM, SRAM, and others
• Tolerant to memory latency
• Includes ‘C’ reference driver and fully-documented API
• Available ready-to-run FPGA Development and Evaluation Platform integrates decoder core with peripherals, memory, interfaces, and essential software
• Companion Transport Stream decoder core available

Efficient and Mature Design

• 200k Gates in 90nm and 75Kbits of internal RAM
• Just 135MHz core clock for Full-HD 4:2:2 1080p/60 decoding
• Production proven in high-volume consumer devices
• Rigorously verified and validated

Applications

The decoder core’s support for MP@HL and 422 makes it an excellent choice for a variety of applications, including:

• Satellite TV/IPTV/Cable Set-top-box
• Blu-ray DVD players
• Video capable portable devices
• Surveillance systems
• Video conferencing
• Video game consoles

Block Diagram

 

FPGA Development & Evaluation Platform

The FPGA Development & Evaluation Platform available with this core implemented in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The MPEG2-D has been rigorously verified using random and directed testing covering corner condition across a wide variety of resolutions. Furthermore, it has been validated using external and internal compliance test suites, as well as streams in ISO13818-4 that are applicable to a MP@HL. The results of the compliance testing are available upon request. Most importantly the core has been multiple times production proven.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Reference driver, API and video player application in C
• Sophisticated shelf-checking HDL Testbench
• Simulation script, vectors, expected results, and timing constraints simulation summary
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, and functional specification.

On this page: Description | Implementation Results | Features | Applications | Block Diagram | FPGA Development & Evaluation Platform | Support | Verification | Deliverables

Download PDF datasheet: ASIC