JPEG Still & Motion
Video Over IP Subsystems
Video & Image Family AVC/H.264, HEVC/H.265 and JPEG Encoders and Decoders
The Video and Image Compression IP Family offers a range of hardware encoders and decoders for JPEG, AVC/H.264, and HEVC/H.265 video. They offer:
- Scalable performance, supporting resolutions beyond Ultra-High Definition (UHD) and/or ultra-high frame rates.
- Extremely small silicon footprint, enabling low-power and economical implementations in FPGAs and ASICs.
- Excellent video quality, even for ultra-low-latency, and/or low-bit-rate video streaming.
After eighteen years providing image and video compression IP—with hundreds of successful customers shipping millions of media products—these are in many ways the best we've ever offered.
Read about them below, see each core's product page, and contact Sales to learn more or get a reference design board for quick evaluation.
Each encoder and decoder in the family satisfies particular needs for performance, power consumption, and silicon area, and offers smart trade-offs of compression degree and quality.
- JPEG and Motion JPEG Encoders and Decoders, in Baseline and Extended (12-bit) variations, offering an economical yet high-quality alternative for moderate levels of video compression,
- H.264/AVC Video Encoders and Decoders, supporting different profiles and featuring the lowest power consumption and smallest silicon area compared to competitive cores, and
- An H.265/HEVC Decoder with versatile support for multiple profiles and video system characteristics.
CAST is one of the longest-running providers of image and video compression IP cores, with hundreds of successful customers shipping millions of media products, beginning in 1998.
Great Video in Lower-Cost Silicon
Consumers increasingly demand advanced video capabilities and now you can build these in without expensive top-ticket silicon.
Achieve, for example:
- Fit 720p@25 fps on an Altera MAX® 10 FPGAs
- Fit 1080p@30 on a Xilinx Zynq®-7020 AP SoC
- Fit UHD/4K@30:
– under 125K ASIC gates, or
– on Altera Stratix V and Xilinx Kintex-7.
- Fit UHD/4K@60 in under 300K gates.
Small size, low power consumption, and high performance make it easy and cost-effective to add media processing to almost any product category using these cores.
Very Low Power Consumption
These dedicated hardware encoders and decoders use dramatically less power than any software or hardware/software codecs with similar capabilities.
They are all designed to use minimal silicon area—one H.264 Encoder needs less than half the area of any competing product—and their smaller footprint saves energy over larger cores.
They also require no or minimal external SDRAM, dramatically reducing a major source of system-wide energy usage. Where they do need external memory, they use on-chip memories to access frequently reused data, to reducing the bandwidth and hence the power related to external memory accesses.
High Performance, 4K/8K Processing
Energy saving doesn’t come at the expense of processing power. The video encoders’ and decoders’ throughput can scale to readily handle 4K, 8K, or higher frame sizes and high frame rates even in modest FPGAs.
The JPEG encoders run ultra-fast, processing up to 32 samples/cycle and easily handling up to UHD/4K video in FPGAs. Multi-channel support and multiple cores is an option for the most demanding systems.
Optimized for the Real World: Low Bit Rates, Ultra-Low Latency, and CBR/VBR Quality
These media codecs are designed to deliver great results in challenging real-world situations.
They achieve excellent results over channels with a very low bit rate—e.g., video streaming over wireless links or network connections—and their ultra-low-latency features ensure viewers don’t perceive any delay or lag in media transmission, a critical factor for many real-time applications.
The encoders are also capable of both Constant Bit Rate (CBR)—for the best quality over a fixed channel—and Variable Bit Rate (VBR)—for the best image or video possible despite changing bandwidth.
The Most Efficient High-Resolution Solutions
Full HD video at 1080p has become a standard expectation, and even that is quickly slipping to UHD at 4K, 8k, or higher. Fortunately cores in this Family give you the most silicon-, energy-, and cost-effective ways to implement high-resolution video compression.
The Motion JPEG capabilities of the image encoders and decoders offers by far the most economical way to process up to 4K video. Yet for moderate compression levels, they provide video quality that’s practically equal to typical H.264, H.265, or JPEG2000 encoders.
The result? Encode UHD/4K video even in smaller ASIC silicon or extremely modest FPGAs. Scalability gets you to even higher resolutions, still with great economies.
For front-to-back processing with even greater savings, use one of our H.264 encoder and decoder combinations, enabling full-duplex video encoding and decoding in less than 200k ASIC gates. (Compared to the 500k gates most competing cores need just for encoding.) This tiny silicon footprint translates to uniquely low silicon cost and power consumption.
Easy System Integration
These encoders and decoders operate in standalone mode: once they are programmed they operate with no need for software control or interaction with the system processor (a further energy savings).
They use industry-standard ARM® AMBA® interfaces for easy SoC compatibility.
The HEVC and JPEG cores use the AMBA® AXI4-Stream interface for pixel and stream data, and APB or AXI4-Lite for register access. Optional Raster Conversion further simplifies integration via an AXI interface to the lines buffer for easy connection to on- or off-chip memory. An optional AHB wrapper for the JPEGs includes a DMA controller.
The H.264 encoders and decoders feature a simple-to-use native interface, plus optional AMBA® AHB, AXI, and AXI-Stream interface wrappers. They come with a raster-to-block converter, which can optionally be instantiated as needed.
Efficient, Adaptable Memory Interfaces
The cores’ memory interfaces also ease integration challenges and reduce system-wide power consumption.
The JPEG cores can handle most processing with just on-chip memory. When used for high-resolution video, then the optional raster-conversion core uses external memory via an AXI4 bus.
This Raster Conversion core as well as the HEVC, and H.264 cores are tolerant to memory access latency—making them suitable for using shared memory resources—and are independent of memory type. They also operate on a different clock than the memory device.
Comparing JPEG Image and Motion JPEG Compression Cores
|Extended Sequential JPEG|
|Motion JPEG Payload|
|Sub-sampling Formats||Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0|
|Image Resolution||16x16 to 64k x 64k|
|Max. Sample Depth||8||12||12||8||12||12|
|Raster Conversion||Included – Optionally Instantiated|
|Color Samples/Cycle||1||1||1 to 32||1||1||1 to 32|
|ASIC Area (eq. Gates)||70k||80k||120k1||65k||75k||110k1|
|Available in RTL Source Code|
|Available as targeted netlist|
|1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample|
Comparing H.264 Video Compression Cores
Low Power Encoders
2 or 1
|2 or 1|
|ASIC (16nm) Performance||UHD/4k@30||UHD/4k@30||1080p60||1080p60||UHD/4k@60||UHD/4k@60|
|Silicon Resources 1||Very Small||Small||Small||Moderate||Moderate–High||Moderate–High|
|Main||High 10 Intra||Constrained
|Slices Types||IDR||IDR, P||IDR, P||IDR||IDR, P||IDR, P|
|Bits per sample||8||8||8||8, 10||8||8|
|Multiple video channels||Optional||Optional||Optional||Optional||Optional|
|CAVLC / CABAC||/||/||/||/||/||/|
|CBR and VBR|
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
|Profile||Constrained Baseline||Constrained Baseline|
|Profile Compatibility||Full||Limited to stream from the H264-E-BPS/BPF, amd BIS cores|
|Additional Features||Interlaced with Main Profile Syntax|
- Very Small <100k Gates, Moderate <500K Gates
Ready for Your Evaluation
Media compression is a challenging technical problem, and no one solution will satisfy the diverse needs of very system design project.
You can study all the features and specs for the encoder and decoder cores you’re considering—and we can answer pre-sales questions and help you fully understand our particular offerings—but often the best way to evaluate these cores is to try them for yourself. We make this easy to do.
Our Video Over IP Subsystems combine H.264 or JPEG cores with everything needed to exercise them, including Raster to Block Conversion, Chroma sub-sampling, UDPIP, RTP, MTS, and DMA controllers. Ready-to-run board kits are available for Altera or Xilinx.
Video over IP Subsystems
Video & Image Reference Designs
Evaluate cores before buying or get a head start on system development with our platforms for JPEG and H.264. Each combines compression cores with peripherals, interconnects, and essential software in ready-to-run FPGA board systems. See the psubsystem pages, or contact CAST Sales for details.
These complete subsystem makes it easy to build in streaming video over Ethernet or Wi-Fi.
They combines H.264 or JPEG compression with essential system functions. For efficient networking, the subsystems use the RTP, MTS-E, and UDP/IP hardware stacks. It can also integrate with CAST or third-party interface MTS or memory controller cores.
Several reference designs are available, running on off-the-shelf Xilinx and Altera boards.
See examples of the reference designs available as well as more specs and detail son the subsystm pages: