Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security

Encryption Primitives
AES, Programmable
Key Expander
Single, Triple

Hash Functions
SHA-3 (Keccak)

JPEG Still & Motion


Lossless & Near-Lossless

Video Over IP Subsystems


Video & Image Family AVC/H.264, HEVC/H.265 and JPEG Encoders and Decoders

The Video and Image Compression IP Family offers a range of hardware encoders and decoders for JPEG, JPEG-LS, AVC/H.264, and HEVC/H.265 video. They offer:

After nineteen years providing image and video compression IP—with hundreds of successful customers shipping millions of media products—these are in many ways the best we've ever offered.

Read about them below, see each core's product page, and contact Sales to learn more or get a reference design board for quick evaluation.




Each encoder and decoder in the family satisfies particular needs for performance, power consumption, and silicon area, and offers smart trade-offs of compression degree and quality.

Included are:

  • JPEG and Motion JPEG Encoders and Decoders, in Baseline and Extended (12-bit) variations, offering an economical yet high-quality alternative for moderate levels of video compression,
  • H.264/AVC Video Encoders and Decoders, supporting different profiles and featuring the lowest power consumption and smallest silicon area compared to competitive cores, and
  • An H.265/HEVC Decoder with versatile support for multiple profiles and video system characteristics.

CAST is one of the longest-running providers of image and video compression IP cores, with hundreds of successful customers shipping millions of media products, beginning in 1998.

Great Video in Lower-Cost Silicon

Consumers increasingly demand advanced video capabilities and now you can build these in without expensive top-ticket silicon.

Achieve, for example:Altera Max 10 chip illustration from Altera July 2015 press release

  • Fit 720p@25 fps on an Intel MAX® 10 FPGAs
  • Fit 1080p@30 on a Xilinx Zynq®-7020 AP SoC
  • Fit UHD/4K@30:
    – under 125K ASIC gates, or
    – on Intel Stratix V and Xilinx Kintex-7.
  • Fit UHD/4K@60 in under 300K gates.

Xilinx Zynq chips photoSmall size, low power consumption, and high performance make it easy and cost-effective to add media processing to almost any product category using these cores.

Very Low Power Consumption

These dedicated hardware encoders and decoders use dramatically less power than any software or hardware/software codecs with similar capabilities.

They are all designed to use minimal silicon area—one H.264 Encoder needs less than half the area of any competing product—and their smaller footprint saves energy over larger cores.

They also require no or minimal external SDRAM, dramatically reducing a major source of system-wide energy usage. Where they do need external memory, they use on-chip memories to access frequently reused data, to reducing the bandwidth and hence the power related to external memory accesses.

High Performance, 4K/8K Processing

Energy saving doesn’t come at the expense of processing power. The video encoders’ and decoders’ throughput can scale to readily handle 4K, 8K, or higher frame sizes and high frame rates even in modest FPGAs.

The JPEG encoders run ultra-fast, processing up to 32 samples/cycle and easily handling up to UHD/4K video in FPGAs. Multi-channel support and multiple cores is an option for the most demanding systems.

Optimized for the Real World: Low Bit Rates, Ultra-Low Latency, and CBR/VBR Quality

These media codecs are designed to deliver great results in challenging real-world situations.

video latency illustration from white paperThey achieve excellent results over channels with a very low bit rate—e.g., video streaming over wireless links or network connections—and their ultra-low-latency features ensure viewers don’t perceive any delay or lag in media transmission, a critical factor for many real-time applications.


The encoders are also capable of both Constant Bit Rate (CBR)—for the best quality over a fixed channel—and Variable Bit Rate (VBR)—for the best image or video possible despite changing bandwidth.

The Most Efficient High-Resolution Solutions

Full HD video at 1080p has become a standard expectation, and even that is quickly slipping to UHD at 4K, 8k, or higher. Fortunately cores in this Family give you the most silicon-, energy-, and cost-effective ways to implement high-resolution video compression.

Motion JPEG frame sequence illustrationThe Motion JPEG capabilities of the image encoders and decoders offers by far the most economical way to process up to 4K video. Yet for moderate compression levels, they provide video quality that’s practically equal to typical H.264, H.265, or JPEG2000 encoders.

The result? Encode UHD/4K video even in smaller ASIC silicon or extremely modest FPGAs. Scalability gets you to even higher resolutions, still with great economies.

For front-to-back processing with even greater savings, use one of our H.264 encoder and decoder combinations, enabling full-duplex video encoding and decoding in less than 200k ASIC gates. (Compared to the 500k gates most competing cores need just for encoding.) This tiny silicon footprint translates to uniquely low silicon cost and power consumption.

Easy System Integration

These encoders and decoders operate in standalone mode: once they are programmed they operate with no need for software control or interaction with the system processor (a further energy savings).

They use industry-standard ARM® AMBA® interfaces for easy SoC compatibility.

The HEVC and JPEG cores use the AMBA®  AXI4-Stream interface for pixel and stream data, and APB or AXI4-Lite for register access. Optional Raster Conversion further simplifies integration via an AXI interface to the lines buffer for easy connection to on- or off-chip memory. An optional AHB wrapper for the JPEGs includes a DMA controller.

The H.264 encoders and decoders feature a simple-to-use native interface, plus optional AMBA® AHB, AXI, and AXI-Stream interface wrappers. They come with a raster-to-block converter, which can optionally be instantiated as needed.

Efficient, Adaptable Memory Interfaces

The cores’ memory interfaces also ease integration challenges and reduce system-wide power consumption.

The JPEG cores can handle most processing with just on-chip memory. When used for high-resolution video, then the optional raster-conversion core uses external memory via an AXI4 bus.

This Raster Conversion core as well as the HEVC, and H.264 cores are tolerant to memory access latency—making them suitable for using shared memory resources—and are independent of memory type. They also operate on a different clock than the memory device.

Comparing JPEG Image and Motion JPEG Compression Cores

  JPEG IP Cores JPEG-LS IP Cores

JPEG Encoder

JPEG Encoder

Ultra Fast Extended
JPEG Encoder

JPEG Decoder

JPEG Decoder

Ultra Fast Extended
JPEG Decoder

JPEG-LS Encoder

JPEG-LS Decoder

Function Encoder Decoder Encoder Decoder
Compression Type  Lossy Lossless/Lossy
Compression Standard JPEG — ISO/IEC 10918-1 JPEG-LS —  ISO/IEC 14495-1
Supported Standard Modes Baseline Sequential DCT Baseline Sequential DCT and Extended Sequential DCT Lossless& NEAR lossless Baseline Sequential DCT and Extended Sequential DCT Lossless & NEAR lossless
Motion JPEG Payload included included included included included included not supported not supported
Sub-sampling Formats Any with up to four components including Single–color, 4:4:4, 4:2:2, 4:2:0
Max. Image Resolution 64k x 64k 64k x 64k > 64k x 64k
Max. Sample Depth 8 12 12 8 12 12 16
Rate control included included included N/A N/A N/A N/A
Raster Conversion Included – Optionally Instantiated Included – Optionally Instantiated N/A
Color Samples/Cycle 1 1 1 to 32 1 1 1 to 32 1 to 32 1 to 32
ASIC Area  (eq. Gates) 70k 80k 120k1 65k 75k 110k1 40K2 40K2
Available in RTL Source Code not supported included included not supported included included included included
Available as targeted netlist included included included included included included included included


1) Silicon Resources for two samples/cycle configuration, and 12 bits per color sample.

2) Silicon Resources for one sample/cycle configuration, and 8 bits per color sample.


Comparing H.264 Video Compression Cores


Low Power Encoders

Fast Encoder

Ultra-Fast Encoder

Low-Power Intra-Only
Baseline Profile Enc

Baseline Profile Encoder

Main Profile Encoder

High Profile Encoder

Baseline Profile Encoder

Throughput (cycles/pixel) 4 4 4 2.5

2 or 1

ASIC (16nm) Performance UHD/4k@30 UHD/4k@30 1080@60 1080@60 UHD/4k@60
Silicon Resources 1 Very Small Small Small Moderate Moderate–High
Profile Constrained
Main High 10 Intra Constrained
Slices Types IDR IDR, P IDR, P IDR IDR, P
Chroma Formats 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0
Bits per sample 8 8 8 8, 10 8
Progressive/Interlaced included/ included included/ included included/ not supported included/ not supported included/ included
Multiple video channels Optional Optional Optional not supported Optional
CAVLC / CABAC included/ not supported included/ not supported not supported/ included included/ not supported included/ not supported
CBR and VBR included included included not supported included
Intra-Refresh N/A included included N/A included
Multiple Slices included included included not supported included


  1. Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.


Decoder Cores

Low Latency Baseline Profile Decoder

Low Power Baseline Profile Decoder

Profile Constrained Baseline Constrained Baseline
Profile Compatibility Full Limited to stream from the H264-E-BPS/BPF, amd BIS cores
Additional Features not supported Interlaced with Main Profile Syntax
Throughput (cycles/pixel)



Silicon Resources1 Moderate Small


  1. Very Small <100k Gates, Moderate <500K Gates

Ready for Your Evaluation

Media compression is a challenging technical problem, and no one solution will satisfy the diverse needs of every system design project.

You can study all the features and specs for the encoder and decoder cores you’re considering—and we can answer pre-sales questions and help you fully understand our particular offerings—but often the best way to evaluate these cores is to try them for yourself. We make this easy to do.

Our Video Over IP Subsystems combine H.264 or JPEG cores with everything needed to exercise them, including Raster to Block Conversion, Chroma sub-sampling, UDPIP, RTP, MTS, and DMA controllers. Ready-to-run board kits are available for Intel or Xilinx.

Video over IP Subsystems

Video & Image Reference Designs

H.264 or J2K board platforms for CAST IP coresEvaluate cores before buying or get a head start on system development with our platforms for JPEG and H.264. Each combines compression cores with peripherals, interconnects, and essential software in ready-to-run FPGA board systems. See the subsystem pages, or contact CAST Sales for details.

These complete subsystem makes it easy to build in streaming video over Ethernet or Wi-Fi.

They combine H.264 or JPEG compression with essential system functions. For efficient networking, the subsystems use the RTP, MTS-E, and UDP/IP hardware stacks. It can also integrate with CAST or third-party interface MTS or memory controller cores.

Several reference designs are available, running on off-the-shelf Xilinx and Intel boards.

See examples of the reference designs available as well as more specs and detail on the subsystem pages:

H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem

H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem

MJPEGOIP-HDE Motion JPEG Video Over IP – HD Encoder Subsystem


video platform




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