Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

 

Profiles

  • Monochrome, Main, Main-10—and optionally the Monochrome 12, Main 4:2:2 10, and Main 4:2:2 12—profiles of ITU-T H.265 | ISO/IEC 23008-2

Performance

  • 1080p60 and 4k/UHD@30 in FPGAs
  • 4K/UHD@60 on high–end FPGAs and ASICs

Video Formats

  • 4:0:0 (Monochrome), 4:2:0, and optionally 4:2:2
  • 8, 10, and optionally 12 bits per color
  • Maximum resolution and frame rate depend on target technology:
    • Full HD (1080p60), and UHD (4K@25) in FPGAs
    • 4K/UHD@60fps in modern ASIC nodes

Ease of Use

  • Full hardwired implementation; standalone, processor-free operation
  • Streaming Interfaces, and Avalon or AMBA AXI interfaces

Low Power

  • Hardwired implementation with application-specific local memories: runs at lower clock frequencies and consumes less power than any software or semi-custom decoder

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Encoders

  • H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
  • H264-E-HIS Intra-Only High Profile Encoder Core
  • H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core

Decoders

  • H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
  • H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core

Subsystems

  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
  • H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem

News Releases

H265-MP-D HEVC/H.265 Main Profile Video Decoder

The H265-MP-D IP core implements a hardware video decoder for the High Efficiency Video Coding (HEVC) compression standard. The core complies with the Monochrome, Main, Main 10, and optionally the Monochrome 12, Main 4:2:2-10, and Main 4:2:2 12  profiles of the standard (ITU-T H.265 | ISO/IEC 23008-2).

The video decoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. The core features streaming-capable AMBA® AXI-S interfaces for the stream and decoded pixel data. A standard AXI4-lite system bus interface gives the host real-time control and status access. An AXI4 memory interface for reading the incoming compressed video and storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture.

The H265-MP-D is a custom hardware accelerator and uses local memories that maximize data reuse and minimize external memory bandwidth, so its power consumption and clock frequency requirements are much lower than any software, or hybrid software/hardware decoder implementation.

The H265-MP-D is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is scan-ready using strictly synchronous with positive-edge clocking and no internal tri-states. The core has been rigorously verified using Fraunhofer’s reference streams and is FPGA proven.

Supported ASIC and FPGA Technologies

The H265-MP-D  is a digital, soft core and can therefore be mapped in any ASIC technology or FPGA device, provided sufficient silicon resources are available for the implementation of the core.
See further implementation information by clicking the technology of your preference below:

ASIC numbers Altera numbers Xilinx numbers

For information on technologies not listed, please contact CAST.

Applications

The H265-MP-D decoder core’s real-time performance and low-power operation makes it an excellent choice for 4K/UHD video broadcasting and streaming applications.

Block Diagram

h265-mp-d Block Diagram

Verification

Standard compliance verified with Fraunhofer HEVC Bitstream Test Suite, and a large collection of HEVC content

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core is available in synthesizable VHDL and FPGA netlist forms. It provides everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.

 

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