- Monochrome, Main, Main-10—and optionally the Monochrome 12, Main 4:2:2 10, and Main 4:2:2 12—profiles of ITU-T H.265 | ISO/IEC 23008-2
- 1080p60 and 4k/UHD@30 in FPGAs
- 4K/UHD@60 on high–end FPGAs and ASICs
- 4:0:0 (Monochrome), 4:2:0, and optionally 4:2:2
- 8, 10, and optionally 12 bits per color
- Maximum resolution and frame rate depend on target technology:
- Full HD (1080p60), and UHD (4K@25) in FPGAs
- 4K/UHD@60fps in modern ASIC nodes
Ease of Use
- Full hardwired implementation; standalone, processor-free operation
- Streaming Interfaces, and Avalon or AMBA AXI interfaces
- Hardwired implementation with application-specific local memories: runs at lower clock frequencies and consumes less power than any software or semi-custom decoder
Call or click.
- H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
- H264-E-HIS Intra-Only High Profile Encoder Core
- H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
- H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
- H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
H265-MP-D HEVC/H.265 Main Profile Video Decoder
The H265-MP-D IP core implements a hardware video decoder for the High Efficiency Video Coding (HEVC) compression standard. The core complies with the Monochrome, Main, Main 10, and optionally the Monochrome 12, Main 4:2:2-10, and Main 4:2:2 12 profiles of the standard (ITU-T H.265 | ISO/IEC 23008-2).
The video decoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. The core features streaming-capable AMBA® AXI-S interfaces for the stream and decoded pixel data. A standard AXI4-lite system bus interface gives the host real-time control and status access. An AXI4 memory interface for reading the incoming compressed video and storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture.
The H265-MP-D is a custom hardware accelerator and uses local memories that maximize data reuse and minimize external memory bandwidth, so its power consumption and clock frequency requirements are much lower than any software, or hybrid software/hardware decoder implementation.
The H265-MP-D is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is scan-ready using strictly synchronous with positive-edge clocking and no internal tri-states. The core has been rigorously verified using Fraunhofer’s reference streams and is FPGA proven.
Supported ASIC and FPGA Technologies
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
For information on technologies not listed, please contact CAST.
The H265-MP-D decoder core’s real-time performance and low-power operation makes it an excellent choice for 4K/UHD video broadcasting and streaming applications.
Standard compliance verified with Fraunhofer HEVC Bitstream Test Suite, and a large collection of HEVC content
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
The core is available in synthesizable VHDL and FPGA netlist forms. It provides everything required for successful implementation, including a sophisticated self-checking testbench, simulation scripts, test vectors, and expected results, synthesis scripts and comprehensive user documentation.