- Ultra-Low Latency H.264 Video Decompression
- Constraint Baseline Profile
- RTP and UDPIP Decapsulation
- Sub-frame latency capable
- Host interface via AXi4-Lite or processor-free UDP-controlled
operation
- AXI4-ST bus for Video & Stream data
- Supports HD – 720p30/60 and Full-HD – 1080p30
Customization Options
- Integration with Video-Outn Controllers (e.g., DVI, HDMI, MIPI-CSI, or SDI)
- Integration with IP-based MAC controllers (e.g., Ethernet or 802.11 WiFi)
Reference FPGA Designs
- Drive display via HDMI, on Xilinx or Intel boards
- Can work with CAST’s H.264 Encoder Subsystem Reference Designs
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Related Products
Subsystems
- H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
Encoders
- H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
- H264-E-HIS Intra-Only High Profile Encoder Core
- H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
Decoders
- H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
- H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
- H265-MP-D HEVC/H.265 Main Profile Video Decoder
Blog Posts
- Choosing the Right IP Cores for Low-Latency Video Streaming
- IoT Phase 2: Design Matters
- White Paper: Understanding—and Reducing—Latency in Video Compression Systems
See more H264 blog posts >>>
White Papers
H264OIP-HDDH.264 Video Over IP – HD Decoder Subsystem
This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complete video streaming products. Hardware reference designs and customization services complete the solution.
The subsystem uses the Low-Latency AVC/H.264 Baseline Profile Decoder Core and the RTP and UDPIP, hardware stacks available from CAST. Flexible interfaces allow easy integration of video, memory, and network controllers, and AXI4-Lite slave interfaces allow a host processor to access all control and status registers. An optional custom logic module allows standalone, processor-free operation and provides access to control and status registers via UDP packets. Video and stream data are transferred among the subsystem’s modules using AXI-Stream, making removing or adding modules straightforward.
The subsystem can decode constraint baseline streams, encapsulated in RTP or plain UDP and features, sub-frame latency (no frame buffers are implemented).
Applications
The H264OIP-HDD Subsystem is suitable for broadcasting, surveillance, industrial, defense, and medical live-streaming applications. The software-free platform consumes significantly less energy than software based solutions, making it ideal as a decompression coprocessor in battery-operated devices with video streaming capabilities.
Reference Designs
A turnkey reference design for Xilinx’s Kintex-7 FPGA KC705 Evaluation Kit is readily available. The reference design integrates the H264OIP-HDD Subsystem with Xilinx’s Ethernet MAC, and uses an HDMI receiver daughter-card for video input. The reference design can be ported to other FPGA boards up on request.
| FPGA Family and Platform | Video-Out |
Stream In |
3rd Party Cores |
Video Formats |
Xilinx Kintex-7, KC705 |
HDMI |
1G Ethernet |
Xilinx TEMAC and DDR3 controller LogiCores |
720p30/60, 1080p@30 |
Customization Services
CAST can integrate the H264OIP-HDE subsystem with your choice of video-in, memory, and network controllers. We can also modify it to support multiple video channels, or different CAST compression cores.
Block Diagram
Comparing H.264 Video Compression Cores
H.264 |
Low Power Encoders |
Fast Encoder |
Ultra-Fast Encoder |
||
|---|---|---|---|---|---|
H264-E-BIS |
H264-E-BPS |
H264-E-MPS |
H264-E-HIS |
H264-E-BPF |
|
| Throughput (cycles/pixel) | 4 | 4 | 4 | 2.5 | 2 or 1 |
| ASIC (16nm) Performance | UHD/4k@30 | UHD/4k@30 | 1080@60 | 1080@60 | UHD/4k@60 |
| Silicon Resources 1 | Very Small | Small | Small | Moderate | Moderate–High |
| Profile | Constrained Baseline |
Constrained Baseline |
Main | High 10 Intra | Constrained Baseline |
| Slices Types | IDR | IDR, P | IDR, P | IDR | IDR, P |
| Chroma Formats | 4:2:0 | 4:2:0 | 4:2:0 | 4:2:0 | 4:2:0 |
| Bits per sample | 8 | 8 | 8 | 8, 10 | 8 |
| Progressive/Interlaced |  / |
/ |
/  |
/ |
/ |
| Multiple video channels | Optional | Optional | Optional | |
Optional |
| CAVLC / CABAC | / |
/ |
/ |
/ |
/ |
| CBR and VBR | |
|
|
|
|
| Intra-Refresh | N/A | |
|
N/A | |
| Multiple Slices | |
|
|
|
|
Notes:
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
H.264 |
H264-D-BP |
H264-LD-BP |
|---|---|---|
| Profile | Constrained Baseline | Constrained Baseline |
| Profile Compatibility | Full | Limited to stream from the H264-E-BPS/BPF, amd BIS cores |
| Additional Features | |
Interlaced with Main Profile Syntax |
| Throughput (cycles/pixel) | 2.5 |
4 |
| Silicon Resources1 | Moderate | Small |
Notes:
- Very Small <100k Gates, Moderate <500K Gates
