RTP Encapsulation for H.264 NAL Streams
- Compliant to RFC 3984 and RFC 6184
- Enables control of RTP packet size
- Supports Fragment Unit Packet
- Run-time programmable maximum stream bytes per RTP packet
- NAL units transmitted in NAL unit decoding order
Easier Integration For Faster Development
- Processor-less, standalone operation
- AMBA® - AXI Interfaces
- AXI4-Lite Control/Status register interfaces
- AXI4-Streaming interfaces for packet data
- Available pre-integrated with:
- H.264 Video Encoder cores from CAST
- UDP/IP Hardware Stack from CAST
- CAST, Intel, Xilinx, or other third-party eMAC core
Call or click.
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- UDPIP UDP/IP Hardware Protocol Stack Core
- MTS-E: MPEG Transport Stream Multiplexing & Encapsulation Engine
- H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
- RTP2H264: Hardware RTP Stack for H.264 Stream Decapsulation
- Choosing the Right IP Cores for Low-Latency Video Streaming
- IoT Phase 2: Design Matters
- White Paper: Understanding—and Reducing—Latency in Video Compression Systems
See more H264 blog posts >>>
H2642RTP Hardware RTP Stack for H.264 Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compliant with RFC 3984 and RFC 6184.
The H2642RTP can be directly connected to the output of an H.264 encoder to output RTP packets, which can subsequently be forwarded for UDP/IP or TCP/IP encapsulation. The hardware stack produces complete RTP packets, without the need for any host-processor assistance. Along with CAST’s UDP/IP hardware stack, the H2642RTP core is ideal for offloading the demanding task of RTP/UDP/IP encapsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs.
The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data can are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.
The H2642RTP core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along H.264 encoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.
The H2642RTP core is suitable for a wide variety systems and devices featuring H.264 video streaming over IP networks. A sample block diagram of such systems is provided below.
The H2642RTP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Comparing H.264 Video Compression Cores
Low Power Encoders
2 or 1
|ASIC (16nm) Performance||UHD/4k@30||UHD/4k@30||1080@60||1080@60||UHD/4k@60|
|Silicon Resources 1||Very Small||Small||Small||Moderate||Moderate–High|
|Main||High 10 Intra||Constrained
|Slices Types||IDR||IDR, P||IDR, P||IDR||IDR, P|
|Bits per sample||8||8||8||8, 10||8|
|Multiple video channels||Optional||Optional||Optional||Optional|
|CAVLC / CABAC||/||/||/||/||/|
|CBR and VBR|
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
|Profile||Constrained Baseline||Constrained Baseline|
|Profile Compatibility||Full||Limited to stream from the H264-E-BPS/BPF, amd BIS cores|
|Additional Features||Interlaced with Main Profile Syntax|
- Very Small <100k Gates, Moderate <500K Gates