Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

RTP Encapsulation for H.264 NAL Streams

  • Compliant to RFC 3984 and RFC 6184
  • Enables control of RTP packet size
    • Supports Fragment Unit Packet
    • Run-time programmable maximum stream bytes per RTP packet
  • NAL units transmitted in NAL unit decoding order

Easier Integration For Faster Development

  • Processor-less, standalone operation
  • AMBA® - AXI Interfaces
    • AXI4-Lite Control/Status register interfaces
    • AXI4-Streaming interfaces for packet data
  • Available pre-integrated with:
    • H.264 Video Encoder cores from CAST
    • UDP/IP Hardware Stack from CAST
    • CAST, Altera, Xilinx, or other third-party eMAC core

Contact Sales
Call or click.
+1 201.391.8300

PDF Datasheets

ASIC

 

Related Products

Compare
Versions

  • H265-MP-D HEVC/H.265 Main Profile Decoder Core
  • UDPIP UDP/IP Hardware Protocol Stack Core
  • MTS-E: MPEG Transport Stream Multiplexing & Encapsulation Engine
  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem

Blog Posts

See more H264 blog posts >>>

H2642RTP Hardware RTP Stack for H.264

Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compliant with RFC 3984 and RFC 6184.

The H2642RTP can be directly connected to the output of an H.264 encoder to output RTP packets, which can subsequently be forwarded for UDP/IP or TCP/IP encapsulation. The hardware stack produces complete RTP packets, without the need for any host-processor assistance. Along with CAST’s UDP/IP hardware stack, the H2642RTP core is ideal for offloading the demanding task of RTP/UDP/IP encapsulation from a host processor, and enables H.264 video streaming even in processor-less SoC designs.

The core is easy to integrate in systems with or without a host processor. H.264 stream and RTP packet data can are input/output via dedicated streaming-capable interfaces, enabling direct connection to hardware video encoders and hardware stacks for UDP or TCP. Status and control registers are accessible by an AXI4-Lite interface.

The H2642RTP core is available in RTL source or as a targeted FPGA netlist. Platforms integrating the core along H.264 encoder, UDP/IP, and eMAC cores, are also available from CAST, and can enable rapid development of video over IP systems.

Applications

The H2642RTP core is suitable for a wide variety systems and devices featuring H.264 video streaming over IP networks. A sample block diagram of such systems is provided below.

Block Diagram

h2642rpt block diagram

Support

The H2642RTP as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Comparing H.264 Video Compression Cores

H.264
Encoder
Cores

Low Power Encoders

Fast Encoder

Ultra-Fast Encoders

H264-E-BIS
Low-Power Intra-Only
Baseline Profile Enc

H264-E-BPS
Low-Power
Baseline Profile Encoder

H264-E-MPS
Low-Power
Main Profile Encoder

H264-E-HIS
Intra-Only
High Profile Encoder

H264-E-BPF
Ultra-Fast
Baseline Profile Encoder

H264-E-MPF
Ultra-Fast,
Main Profile Encoder

Throughput (cycles/pixel) 4 4 4 2.5

2 or 1

2 or 1
ASIC (16nm) Performance UHD/4k@30 UHD/4k@30 1080p60 1080p60 UHD/4k@60 UHD/4k@60
Silicon Resources 1 Very Small Small Small Moderate Moderate–High Moderate–High
Profile Constrained
Baseline
Constrained
Baseline
Main High 10 Intra Constrained
Baseline
Main
Slices Types IDR IDR, P IDR, P IDR IDR, P IDR, P
Chroma Formats 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0
Bits per sample 8 8 8 8, 10 8 8
Progressive/Interlaced included/ included included/ included included/ not supported included/ not supported included/ included included/ not supported
Multiple video channels Optional Optional Optional not supported Optional Optional
CAVLC / CABAC included/ not supported included/ not supported not supported/ included included/ not supported included/ not supported not supported/ included
CBR and VBR included included included not supported included included
Intra-Refresh N/A included included N/A included included
Multiple Slices included included included not supported included included

Notes:

  1. Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.

 

H.264
Decoder Cores

H264-D-BP
Low Latency Baseline Profile Decoder

H264-LD-BP
Low Power Baseline Profile Decoder

Profile Constrained Baseline Constrained Baseline
Profile Compatibility Full Limited to stream from the H264-E-BPS/BPF, amd BIS cores
Additional Features not supported Interlaced with Main Profile Syntax
Throughput (cycles/pixel)

2.5

4

Silicon Resources1 Moderate Small

Notes:

  1. Very Small <100k Gates, Moderate <500K Gates

 

 

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