• Features
• More Info

Supported H.264 Profiles

• Main and Constrained-Baseline
• Intra versions of both the above

Supported Video Rormats

• 4:2:0 YCbCr input with 8 bits per color sample
• Annex B NAL byte stream output
• Constant Bit Rate (CBR) or variable bit rate Constant Quality (CQP) modes

High Performance

• Level up to 5.2,
• Up to 240 MBits/s for CAVLC
• Up to 135 MBits/s for CABAC
• High throughput
• 2.5 clocks/pixel for 4:2:0

Advanced Rate Control

• Advanced rate control operates on sub-frame basis, uses micro-adjustments per MB, and employs run-time adaptive models
• Optimizes rate distortion and perceived video quality
• Respects decoder buffer: HRD CPB compliant CBR output
• Provides uniform quality and rapidly adopts to temporal and spatial video variations
• Allows for end-to-end latency control down to sub-frame levels

Ease of Integration

• CPU-less, stand-alone operation
• No need for external raster conversion
• Support for planar, interleaved and macroblock input scan
• Flexible external memory interface
• Independent of memory type
• Low bandwidth requirements and tolerant to latencies, for shared memory architectures
• Flexible video input and stream output interfaces
• Flow-controllable, streaming-capable Avalon-ST interfaces
• Optional wrappers for direct connection to an AMBA® AHB or AXI SoC bus
• Run-time tunable operation and on-the-fly target rate changes

Encoding Tools

• CABAC or CAVLC Encoding
• Motion Estimation
• Optimal, Full-Search
• 32x20 or higher search area; down to ¼ pel accuracy
• Variable block size; up to four motion vectors per MB
• Sophisticated block skipping for fewer motion artifacts in low bit rates
• All 16x16 and 4x4 luma, and all chroma intra prediction modes
• In-Loop deblocking filter
• Multiple slices for error resilience
• Optional thresholding of quantized transform coefficients

PDF Datasheets

ASIC
Altera, Xilinx

Options

AHB Compression Core Bus Bridge

Related Products

Compare
Versions

• H264-HP-E H.264/AVC High Profile HD & ED VIdeo Encoder Core
• H264-BP-E H.264/AVC BAseline Profile HD & ED Video Encoder core
• H264-INTRA-D H.264/AVC Intra Video Decoder Core
• H264-AP H.264 Video Encoding Application Platform
• CCBB-AHB AHB Compression Core Bus Bridge – adds an AHB interface to the H264-MP-E core
• H2642RTP Hardware RPT Stack for H.264      
• UDPIP UDPIP UDP/IP Hardware Protocol Stack Core      

Related Information

News Release

• 05/16/13, Ultra-Low Latency H.264 Video Encoding Now Available from CAST
• 01/26/11, CAST adds H.264 Main Profile Video Encoder Core to Compression IP Family

Application Platform

Evaluate this core in hardware with the complete, ready-to-run, H.264 Application Platform package.

H.264 IP Core H264-MP-E H.264/AVC Main Profile HD & ED Video Encoder Core

This H.264-MP-E IP core implements a video encoder compatible to the Main profile of the H.264 standard, also known as MPEG-4 Part 10.

The H.264-MP-E core can encode at Full HD (1080p@30) or higher rates, even in low-cost FPGAs. Employing innovative techniques and algorithms, it provides quality beyond typical H264 hardware Main Profile encoders. The core can perform constant bit rate (CBR) compression that produces the highest possible quality while fitting the output to a specified bit rate, or constant-Qp, variable bit rate (VBR) compression to achieve a uniform quality level among frames. Under CBR mode, the sophisticated rate control algorithm also enables control over the end-to-end (encoding/decoding) latency, which can be configured to ultra-low, sub-frame levels.

The H.264-MP-E core can be configured to operate on Intra-Only mode, offering compression efficiency superior than this of JPEG and competitive to this of JPEG2000. Under this configuration the requirements for an external memory can be eliminated, the core’s size is cut to half, and the output stream remains H264 compliant. With Intra-only compression each frame is coded independently, allowing for smaller processing delays, easier video editing, and enhanced error resilience.

The core is designed for ease and trouble-free integration. It can automatically convert incoming frames to the macroblock format required by the H.264 standard, and it outputs the standard H.264 Annex B NAL byte stream. Furthermore, the core operates independently from a host processor and is run-time programmable for user control over compression parameters and bit rate options. Finally, a flexible external memory interface makes the core independent of memory type—supporting SRAM, SDRAM, or DDRAM—and more tolerant to the large delays and latencies typically present on a shared bus architecture.

The core is designed for reuse and reliability, and has been rigorously verified and FPGA proven. System integration is facilitated by the core’s complete verification environment, with additional aids for system-on-chip simulation available such as a software bit-accurate model (BAM) and a complete hardware/software reference design system.

See representative implementation results (each in a new pop-up window):

Applications

The H264-MP-E core efficiently handles extended definition (ED) through high definition (HD) video, and is suitable for a range of applications including surveillance and monitoring, video conferencing, and streaming video on demand.

Block Diagram

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:

• HDL RTL source code (ASICs) or post-synthesis netlist (FPGAs)
• Sophisticated self-checking Testbench  (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model and test vector generator
• Synthesis scripts (ASIC) or place and route script (FPGAs)
• Simulation script, vectors and expected results
• Comprehensive user documentation, including detailed specifications and a system integration guide

Evaluation

The video encoder’s extremely high visual quality is best evaluated by compressing examples of an application’s actual input video. There are three ways to do this.

• Work directly with CAST’s video compression engineers,
• Use the available BAM for software simulation, or
• Use the available H264-AP H.264 Application Platform, a board and software package combining the H.264 Encoder, memory and controller, and other IP cores with software drivers and a graphical user interface for H.264 control.

Please contact CAST Sales to discuss your specific project requirements (sales@cast-inc.com) (+1 201.391.8300).