- Decodes streams produced by the H264-E-BPS, H264-E-BPF, and H264-E-BIS cores
- Progressive or Interlaced, 4:2:0 YCbCr with 8 bits per color sample
- Single-channel SD, ED, and Full-HD capable even in low-cost FPGAs
- Optional multichannel decoding
Small and Low-Power
- Less than 70 KGates and 60k bits of RAM
- Less than half the typical silicon footprint and small external memory bandwidth mean it uses less power than competitive hardware H.264 decoders
- Consumes much less power than any equivalent software or software-hardware decoder
Ease of Integration
- Zero CPU overhead, stand-alone operation
- Flexible external memory interface. Uses separate clock, is independent of memory type and tolerant to latencies
- AMBA® Interface Options: DMA-capable AMBA® AHB, AXI or AXI-Streaming
Supported Coding Tools
- I and P Slices
- Single Reference Frame
- Motion vector up to –32.00/+31.75 pixels down to ¼ pel accuracy
- All intra16x16 and most intra 4x4 modes
- Multiple slices per frame
- Block skipping
- Deblocking filter
Call or click.
- H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
- H264-E-HIS Intra-Only High Profile Encoder Core
- H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core
- H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
- H265-MP-D HEVC/H.265 Main Profile Video Decoder
- H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
- H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem
- Choosing the Right IP Cores for Low-Latency Video Streaming
- IoT Phase 2: Design Matters
- White Paper: Understanding—and Reducing—Latency in Video Compression Systems
See more H264 blog posts >>>
H264-LD-BPLow-Power AVC/H.264 Baseline Profile Decoder Core
The H264-LD-BP IP core implements a silicon and energy efficient hardware video decoder able to process H.264 streams produced by the H264-E-BPS, H264-E-BPF and H264-E-BIS video encoder cores available from CAST.
The H264-LD-BP is extremely small, requiring less than 70K gates and about 60k bits of infernal memory. Its small silicon footprint, low bandwidth requirements, and zero software overhead enable extremely cost-effective and low-power ASIC and FPGA implementations.
The H264-LD-BP is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. The decoder’s memory interface—used to store reconstructed video data—is extremely flexible: it operates on a separate clock domain, is independent from the external memory type and memory controller, and is tolerant to large latencies. The decoder reports decompressed video parameters, detects and reports bit stream errors to the system, and simplifies video cropping at its output. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.
Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding/decoding subsystems. These integrate the decoder core with video encoders, video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.
The H264-LD-BP IP core is designed using with industry best practices and has been multiple times production proven. Its deliverables include a complete verification environment and a bit-accurate software model.
See representative implementation results (each in a new pop-up window):
The core is available in source-code HDL (Verilog or VHDL) or as a targeted netlist, and its deliverables include everything required for successful implementation
- Source-code HDL (Verilog or VHDL) (ASICs) or as a targeted netlist (FPGAs)
- Sophisticated self-checking Testbench
- Synthesis scripts.
- Simulation script, vectors and expected results.
- Software (C++) Bit-Accurate Model and test-vector generator
- Comprehensive user documentation
Silicon Resources Utilization
The H264-LD-BP synthesizes to less than 70k gates and also requires about 60k bits of internal memory.
Potential customers can readily evaluate the video decoder’s low latency characteristics by using the Video over IP reference design with compressed stream captured over Ethernet, and decoded video driving an HDMI interface.
H.264 Cores Family
The H264-LD-BP is one member of the family of H.264 cores that CAST offers. The following tables summarize the family members and highlight their basic features.
Low Power Encoders
2 or 1
|2 or 1|
|ASIC (16nm) Performance||UHD/4k@30||UHD/4k@30||1080p60||1080p60||UHD/4k@60||UHD/4k@60|
|Silicon Resources 1||Very Small||Small||Small||Moderate||Moderate–High||Moderate–High|
|Main||High 10 Intra||Constrained
|Slices Types||IDR||IDR, P||IDR, P||IDR||IDR, P||IDR, P|
|Bits per sample||8||8||8||8, 10||8||8|
|Multiple video channels||Optional||Optional||Optional||Optional||Optional|
|CAVLC / CABAC||/||/||/||/||/||/|
|CBR and VBR|
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
|Profile||Constrained Baseline||Constrained Baseline|
|Profile Compatibility||Full||Limited to stream from the H264-E-BPS/BPF, amd BIS cores|
|Additional Features||Interlaced with Main Profile Syntax|
- Very Small <100k Gates, Moderate <500K Gates