H264-LD-BP Core — ASIC Implementation Results

The H264-LD-BP can be mapped to any ASIC technology and optimized to suit the particular project’s requirements. The following table provides sample implementation data for a single H264-LD-BP. These sample implementation figures do not represent the highest speed or smallest area possible for the core. Note that under certain conditions two or more H.264-LD-BP cores can be combined to decode streams produced by the H264-E-BPF core. Please contact CAST to get characterization data for your target configuration and technology.

Target
Technology
Logic
(Gates)
Memory
Bits
Freq.
(MHz)
Throughput
(Mpixels/sec)
Video
Format
TSMC 16nm 55k
58k 1,000 250 UHD/4k@30fp
TSMC 40nm 60k
58k 500 200 1080p60

 

close window