H.264 IP Core H264-INTRA-D H.264 Intra Video Decoder Core

Implements a hardware intra-only video decoder that conforms to the Constrained Baseline Profile, Main Profile, or High 4:2:2 Profile of the H.264/AVC standard (also known as MPEG-4 Part 10).

The core can decode streams at the 4.2 level of the standard, which includes Full-HD, 1920x1080 video encoded at 50 Mbits/second. Optional High 4:2:2 Profile support enables the core to decode streams at rates up to 100 MBits/second.

The video decoder is designed for straightforward, trouble-free SoC integration. It can operate on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. A standard AMBA® APB system bus interface gives the host real-time control and status access. A flexible memory interface for reading the incoming compressed video and storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture. Furthermore, the core’s decoded image storage can be configured to match the input video stream, allowing the minimum amount of memory to be allocated for each specific stream.

The core is designed for reuse and reliability, and has been rigorously verified and FPGA proven. A complete ‘C’ reference driver and fully-documented API facilitate system integration. An optional FPGA-based reference system using the core provides a complete development environment for evaluation and early software development.

Implementation Results

The H264-Intra-D core was developed using best-in-class design principles and is very efficient in resource usage and clock rates. The core synthesizes to about 175k gates and 65 Kbits of memory. Please contact CAST for detailed area and timing results for any specific technology you require.

Applications

The decoder core’s support for multiple H.264 profiles and high-resolution, 4.2 level video makes it an excellent choice for a variety of applications, including:

• Satellite TV/IPTV/Cable Set-top-box
• Blu-ray DVD players
• Video capable portable devices
• Surveillance systems
• Video conferencing
• Video game consoles

Block Diagram

Support

The core as delivered is warranted against defects for 90 days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The H264-Intra-D has been rigorously verified using random and directed testing covering corner condition across a wide variety of resolutions. Furthermore, it has been validated using external and internal compliance test suites. The results of the compliance testing are available upon request. Extensive interoperability testing has also been conducted using a wide variety of shipping encoder products.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Reference driver, API and video player application in C
• Sophisticated shelf-checking HDL Testbench
• Simulation script, vectors, expected results, and timing constraints simulation summary
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including a fully documented API, and functional specification.

FPGA Development & Evaluation Platform

The FPGA Development & Evaluation Platform available with this core implemented in an FPGA allows quick and cost-effective evaluation and early software prototyping.

The ready-to-run platform includes a 32-bit host processor capable of running custom applications, DVI and other built-in interfaces, and a peripherals suite running a flash-based ROM monitor that loads at power-up.

The ROM monitor allows for the development and download of customer specific application code developed using GCC, enabling simultaneous hardware and software evaluation.