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AMBA AHB Multimedia Interface Core
Related Information
News Releases
06/14/10 CAST H.264 Video Encoder IP Core Now More Flexible, Faster, and Easier to Integrate
07/14/09 CAST Releases H.264 IP Core for Highest Quality HD Video Compression
Reference
Design
System
Evaluate this core in hardware with the complete, ready-to-run, H.264 Reference Design System package.
H.264 IP Core H264-E H.264/AVC HD & SD Video Encoder Core
On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables | Evaluation
This H.264 IP core implements a video encoder in hardware that uses the Baseline profile H.264 Advanced Video Coding (AVC) standard (up to level 4.1), also known as MPEG-4 Part 10. The core receives a stream of video frames, automatically converts them to the macroblock format required by the H.264 standard if necessary, compresses the video and outputs the standard H.264 Annex B NAL byte stream.
The H.264 core can process up to 1080p HDTV video. It can perform constant bit rate (CBR) compression that produces the highest possible quality while fitting the output to a specified bit rate, or variable bit rate (VBR) compression to always achieve a specified quality level. The proprietary CBR algorithm used by the core provides user-controlled granularity, and it runs faster and produces video that is visually and measurably superior to competing solutions.
The core operates independently from a host processor—resulting in a smaller and more power efficient implementation than other approaches—and is run-time programmable for user control over compression parameters and bit rate options. A flexible external memory interface makes the core independent of memory type—supporting SRAM, SDRAM, or DDRAM—and more tolerant to the large delays and latencies typically present on a shared bus architecture.
The core is designed for reuse and reliability, and has been rigorously verified. System integration is facilitated by the core’s complete verification environment, with additional aids for system-on-chip simulation available such as a software bit-accurate model (BAM) and a complete hardware/software reference design system.
See representative implementation results (each in a new pop-up window):
Applications
The H264-E core efficiently handles standard definition (SD) through high definition (HD) video, and is suitable for a range of applications including surveillance and monitoring, video conferencing, and streaming video on demand.
Features
CAST H.264 Output Tracks Reference Standard Quality Measures
The quality of the video produced by an H.264 encoder is very dependent on the specific clip being encoded. This quality is typically assessed by running the reference standard JM software H.264 encoder on the same clip. Peak signal-to-noise ratio (PSNR) values measure the perceived quality at different levels of compression (for different transmission rates).
In this challenging 720p Shuttle Launch clip -- and in hundreds of other tests with a variety of clips -- the baseline CAST H.264-E encoder IP core produces quality very close to that of the JM standard. It does so using considerably fewer resources than competing cores supporting higher level profiles. Contact us to see additional benchmarks and learn more about the superior quality results of our H.264 encoder core. (Click image for high-res version.)
H.264 Video Encoding
- Fully compliant to the ISO/IEC 14496-10/ITU-T H.264 baseline specification (MPEG-4 Part 10, Advanced Video Coding)
- Profile level up to 4.1
- Flexible 4:2:0 video input
- Planar scan
- Interleaved scan
- Macroblock scan
- Automatically converts video input to the macroblock format required for H.264 processing
- Produces a ITU-T H.264 Annex B compliant NAL video byte stream
- Compression efficiency from QCIF up to HD resolutions
- Programmable bit rate control
- Variable bit rate compression
- Constant bit rate compression
- Single reference frame
- Advanced Inter-Prediction
- Quarter pel accuracy
- Variable block size
- Block skipping
- 32x32 search area (motion vector up to –16.75/+15.75 integer pels in both dimensions)
- Advanced intra prediction modes
- All four Intra 16x16 luma prediction modes
- All four Intra prediction 8x8 chroma modes
- All nine Intra 4x4 luma prediction modes
- Advanced Intra prediction in Inter slices
- Multiple slices for enhanced error resilience
- Advanced mode selection for superior compression and quality
- CAVLC Encoding
- In-Loop deblocking filter
System Integration
- Processor-independent, stand-alone operation
- Flexible external memory interface and independence from external memory type
- Low latency
- Bit Accurate Model
- Available Reference Design System hardware/software package
Block Diagram
Functional Description
The H264-E core is a hardware implementation of the H.264 baseline video compression algorithm, designed to process up to 1080p HDTV video. It consists of a number of functional blocks, as shown in the diagram and described here.
For each block of pixels, the Intra Prediction unit generates a suitable prediction. In the case of P-frames, the Motion Estimation Unit also generates a prediction, operating with quarter-pixel accuracy. The prediction cost of each unit is estimated using Lagrange multipliers, and the best is selected for encoding.
The residual information is calculated from the difference between the current block and the prediction. Constant or variable bit rate calculations are applied. The data is then transformed and quantized to be encoded by the Entropy Coding unit.
The transformed, quantized residual is also used to reconstruct a reference frame, which will be used during the encoding of future P-frames. This is achieved by inverse quantization and transformation of the residual, which is then added back to the prediction. Finally, the reconstructed frame is filtered before being stored back in the external memory.
The core can perform macroblock skipping that is important for low data rate applications, and suport multiple slices that enhances error resilience of the compressed stream.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The ASIC version includes:
- HDL RTL source code
- Synthesis scripts
- Simulation script, vectors and expected results
- Sophisticated HDL Testbench
- Software (C++) Bit-Accurate Model (BAM)
- Comprehensive user documentation, including detailed specifications and a system integration guide
Evaluation
The video encoder’s extremely high visual quality is best evaluated by compressing examples of an application’s actual input video. There are three ways to do this.
Work directly with CAST’s video compression engineers,
Use the available BAM for software simulation, or
Use the available H264-REF H.264 Reference Design System, a board and software package combining the H.264 Encoder, memory and controller, and other IP cores with software drivers and a graphical user interface for H.264 control.
On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables | Evaluation
Download PDF datasheets for more info: ASIC | Altera | Xilinx
This core developed by the multimedia experts at Alma
Technologies S.A.
