Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Compact, low-power AVC/H.264 encoder, suitable for applications requiring moderate-levels of compression

Encoding Features

  • High 10 Intra profile with CAVLC entropy coding

  • All 4x4 and 16x16 intra prediction modes except plane prediction

  • 8-bit and 10-bit color depth and 4:2:0 chroma sampling format

  • VBR: variable bitrate encoding with a fixed quantization parameter (QP)

  • CBR – Constant bitrate encoding with external adjustment of QP at frame boundaries

Ease of Integration

  • Zero CPU overhead, stand-alone operation for VBR mode

  • Requires no external, off-chip memory

  • FIFO-like pixel-in and stream-out interfaces, optionally bridged to AXI-Stream or Avalon Streaming

  • Optionally delivered with raster-to-block converter module

Performance and Size

  • 2.35 clock cycles per pixel

  • Up to UHD/4K in ASICs; and up to Full-HD in FPGAs

  • 220k eq. Gates, and 280K to 420k bits of SRAM (depending on configuration)

Compression Efficiency

  • Better than (Motion) JPEG, equivalent, or better than (Motion) JPEG200

Contact Sales
Call or click.
+1 201.391.8300

Downloads (PDFs)

Related Products

Compare
Versions

Encoders

  • H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
  • H264-E-BPF Ultra-Fast AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core

Decoders

  • H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
  • H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
  • H265-MP-D HEVC/H.265 Main Profile Video Decoder

Subsystems

  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
  • H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem

News Releases

Blog Posts

See more H264 blog posts >>>

H264-E-HIS H.264, High 10 Intra Profile Encoder Core

The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a small silicon footprint—approximately 220K gates and 280K to 420K bits of SRAM—and requires no external memory (e.g. off-chip DRAM) allowing for very cost-effective and low-power ASIC or FPGA implementations.

Despite its small size, the H264-E-HIS implements a highly efficient intra-frame compression engine. When measured at the same bit rate, the video quality of the compressed streams it produces exceeds that of Motion-JPEG and is similar to or better than the video quality of Motion JPEG2000. Being intra-coded, the produced H.264 streams feature high error resilience, allow for random access in the compressed stream, and ease video editing. Furthermore, the core can output both Variable Bit-Rate (VBR) and Constant Bit Rate (CBR) video. The core autonomously produces VBR streams, while CBR streams can be produced when quantization is externally adjusted on frame boundaries.

The core was designed for ease of use and integration. Once initially programmed, it compresses an arbitrary number of frames without any assistance from the host processor. Moreover, the core does not require any external memory (such as an off-chip DRAM) for its operation, and features FIFO-like flow-controllable interfaces for the pixel and compressed stream data. The core is optionally delivered with a raster-to-block converter, and bridges to AXI-Stream or Avalon Streaming interfaces.

Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding subsystems. These integrate the encoder core with video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.

The H264-E-BPF IP core is designed using with industry best practices and has been production proven multiple times. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Block Diagram

h264-e-his H.264, High 10 Intra Profile Encoder Core Block Diagram

Deliverables

The H264-E-HIS IP core is available in source-code VHDL or as a targeted netlist. Its deliverables include a sophisticated self-checking testbench, sample synthesis and simulation scripts, a software (Bit-Accurate) model, and comprehensive user documentation.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

 

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