High 10 Intra profile with CAVLC entropy coding
All 4x4 and 16x16 intra prediction modes except plane prediction
8-bit and 10-bit color depth and 4:2:0 chroma sampling format
VBR: variable bitrate encoding with a fixed quantization parameter (QP)
CBR – Constant bitrate encoding with external adjustment of QP at frame boundaries
Ease of Integration
Zero CPU overhead, stand-alone operation for VBR mode
Requires no external, off-chip memory
FIFO-like pixel-in and stream-out interfaces, optionally bridged to AXI-Stream or Avalon Streaming
Optionally delivered with raster-to-block converter module
Performance and Size
2.35 clock cycles per pixel
Up to UHD/4K in ASICs; and up to Full-HD in FPGAs
220k eq. Gates, and 280K to 420k bits of SRAM (depending on configuration)
Better than (Motion) JPEG, equivalent, or better than (Motion) JPEG200
Call or click.
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H264-E-HIS H.264, High 10 Intra Profile Encoder Core
The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a small silicon footprint—approximately 220K gates and 280K to 420K bits of SRAM—and requires no external memory (e.g. off-chip DRAM) allowing for very cost-effective and low-power ASIC or FPGA implementations.
Despite its small size, the H264-E-HIS implements a highly efficient intra-frame compression engine. When measured at the same bit rate, the video quality of the compressed streams it produces exceeds that of Motion-JPEG and is similar to or better than the video quality of Motion JPEG2000. Being intra-coded, the produced H.264 streams feature high error resilience, allow for random access in the compressed stream, and ease video editing. Furthermore, the core can output both Variable Bit-Rate (VBR) and Constant Bit Rate (CBR) video. The core autonomously produces VBR streams, while CBR streams can be produced when quantization is externally adjusted on frame boundaries.
The core was designed for ease of use and integration. Once initially programmed, it compresses an arbitrary number of frames without any assistance from the host processor. Moreover, the core does not require any external memory (such as an off-chip DRAM) for its operation, and features FIFO-like flow-controllable interfaces for the pixel and compressed stream data. The core is optionally delivered with a raster-to-block converter, and bridges to AXI-Stream or Avalon Streaming interfaces.
Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding subsystems. These integrate the encoder core with video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.
The H264-E-BPF IP core is designed using with industry best practices and has been production proven multiple times. Its deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
The H264-E-HIS IP core is available in source-code VHDL or as a targeted netlist. Its deliverables include a sophisticated self-checking testbench, sample synthesis and simulation scripts, a software (Bit-Accurate) model, and comprehensive user documentation.
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.