H264-E-HIS Core — XILINX FPGA Results

The H264-E-HIS can be mapped to any Xilinx Family (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation data for the core under its default configuration.  Please contact CAST to get characterization data for your target configuration and technology.

  720p@30 720p60 1080p@30
ARTIX-7 included included included
KINTEX-7 included included included


included included included
LUTs 1 24.4K
BRAMs 120 RAMB18, 14 RAMB36
DSPs 33
1. Exact resource requirements and max performance depend on target device
2: Indicated performance may not be supported at devices of all speed grades

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