H264-E-BPS and H264-E-BIS Core — XILINX FPGA Results

The H264-E-BPS can be mapped to any Xilinx Family (provided sufficient silicon resources are available) and optimized to suit the particular project’s requirements. The following table provides sample implementation data for the core configured under its default configuration (H264-E-BPS) and for the intra-only version for the core (H264-E-BIS). Please contact CAST to get characterization data for your target configuration and technology.

  H264-E-BPS H264-E-BIS
720p@30 1080p@30 720p@30 1080p@30
ARTIX-7 included not supported included not supported
KINTEX-7 included not supported included not supported


included included included included
LUTs 1 16K 8k
Slices 1 4.8k 2.6k
BRAMs 18 3
DSPs 4 4

1: Exact resources usage and max performance depend on target device
2: Indicated performance may not be supported at devices of all speed grades

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