Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream

Octal SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Data Link Controllers
16450S, 16550S, 16750S

PCI Express
Family Overview
x1/x4, x8
application interface

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

Ultra-fast, low-latency, production-proven, AVC/H.264 encoder
  • Options for one or two cycles per pixel
  • UHD/4K and very high frame rates at lower resolutions in ASICs and FPGAs

Standard Support

  • ISO/IEC 14496-10/ITU-T H.264 Constrained Baseline Profile specification
  • Interlaced Video using Main Profile syntax
  • Output Annex B NAL byte stream decodable by Baseline, Main, and High Profile decoders

Input Video Formats

  • Progressive or Interlaced, 4:2:0 YCbCr input with 8 bits per color sample
  • Up to UHD/4k in ASICs; up to Full-HD in FPGAs
  • Optional multichannel encoding

Low Latency and Low Bit Rates with Fewer Artifacts

  • Constant Bit-Rate (CBR) output for smaller stream buffers and end-to-end latency
  • Advanced rate control regulates Qp multiple times within a frame, and rapidly responds to temporal or spatial video variations
  • Enables artifacts-free Intra-Refresh to eliminate bit rate peaks of I frames
  • Block skipping, Quantized coefficients thresholding, and in-loop deblocking filter improve quality at low bit rates

Small and Low Power

  • 250K gates and 375 kbits of RAM (for two-cycles-per-pixel configutation)
  • Uses less power than equally capable hardware H.264 encoders thanks to its smaller silicon footprint and small external memory bandwidth
  • Consumes much less power than any equivalent software, or software-hardware encoder

Ease of Integration

  • Zero CPU overhead, stand-alone operation
  • Flexible external memory interface uses separate clock, is independent of memory type and tolerant to latencies

Contact Sales
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Downloads (PDFs)

Related Products



  • H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
  • H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
  • H264-E-HIS Intra-Only High Profile Encoder Core
  • H264-E-MPF Ultra-Fast AVC/H.264 Main Profile Encoder Core


  • H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
  • H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
  • H265-MP-D HEVC/H.265 Main Profile Video Decoder


  • H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
  • H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem

News Releases

Blog Posts

See more H264 blog posts >>>

H264-E-BPFUltra-Fast AVC/H.264 Baseline Profile Encoder

The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an ultra-high throughput, UHD/4K capable hardware encoder that is optimized for ultra-low-latency video streaming at low bit rates.

The H264-E-BPF encoder requires less silicon area than most equally capable hardware H.264 encoders—approximately 250K gates—allowing for very cost-effective implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable high-throughput H.264 coding at an extremely low energy cost. The encoder is able to process UHD/4K video when mapped on modern ASIC technologies, and Full-HD when mapped on FPGAs.

Despite being small, the H264-E-BPF produces high-quality video, especially at low bit rates, and is suitable for systems with low latency requirements. It uses constant quantization to output video streams of Variable Bit-Rate (VBR), or automatically regulates quantization multiple times within a frame to output Constant Bit-Rate (CBR) streams. In CBR mode it responds rapidly to temporal or spatial changes in the video content. This can be combined with an artifacts-free Intra-Refresh coding implementation to effectively eliminate bit rate peaks, while preserving the periodic intra-coded references. As a result, the stream buffers can be smaller than those typically required, and the end-to-end latency can be brought down to frame or sub-frame levels. Video quality at  low-bit rates is preserved, as the encoder intelligently uses block-skipping and quantization coefficient thresholding to reduce bit rate at minimal quality loss, and uses the in-loop deblocking filter to eliminate the blocking artifact.

The core was designed for ease of use and integration. Once initially programmed, it operates without any assistance from the host processor. The encoder’s memory interface is extremely flexible: it operates on a separate clock domain, is independent from the external memory type and memory controller, and is tolerant to large latencies. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.

Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding subsystems. These integrate the encoder core with video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.

The H264-E-BPF IP core is designed using with industry best practices and has been production proven multiple times. Its deliverables include a complete verification environment and a bit-accurate software model.

See representative implementation results (each in a new pop-up window):

ASIC numbers Altera numbers Xilinx numbers

Block Diagram

h264-e-bpf Ultra-Fast AVC/H.264 Baseline Profile Encoder Block Diagram

Coding Tools

Silicon Resources Utilization

The H264-E-BPF core’s silicon resources requirements depend on its configuration. A two cycles per pixel configuration synthesizes to approximately 250K gates and 375 kbits of memory, and a one cycle per pixel configuration synthesizes to 400K gates and 600 kbits of memory.  


The core is available in source-code HDL (Verilog or VHDL) or as a targeted netlist, and its deliverables include everything required for successful implementation:


Potential customers can readily evaluate the video encoder’s compression efficiency can be evaluated by using: 

Please contact CAST to arrange for your evaluation preference. 

H.264 Cores Family

The H264-E-BPS is one member of the family of H.264 encoder cores that CAST offers. The following table summarizes the family members and highlights their basic features.


Low Power Encoders

Fast Encoder

Ultra-Fast Encoders

Low-Power Intra-Only
Baseline Profile Enc

Baseline Profile Encoder

Main Profile Encoder

High Profile Encoder

Baseline Profile Encoder

Main Profile Encoder

Throughput (cycles/pixel) 4 4 4 2.5

2 or 1

2 or 1
ASIC (16nm) Performance UHD/4k@30 UHD/4k@30 1080p60 1080p60 UHD/4k@60 UHD/4k@60
Silicon Resources 1 Very Small Small Small Moderate Moderate–High Moderate–High
Profile Constrained
Main High 10 Intra Constrained
Slices Types IDR IDR, P IDR, P IDR IDR, P IDR, P
Chroma Formats 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0 4:2:0
Bits per sample 8 8 8 8, 10 8 8
Progressive/Interlaced included/ included included/ included included/ not supported included/ not supported included/ included included/ not supported
Multiple video channels Optional Optional Optional not supported Optional Optional
CAVLC / CABAC included/ not supported included/ not supported not supported/ included included/ not supported included/ not supported not supported/ included
CBR and VBR included included included not supported included included
Intra-Refresh N/A included included N/A included included
Multiple Slices included included included not supported included included


  1. Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.


Decoder Cores

Low Latency Baseline Profile Decoder

Low Power Baseline Profile Decoder

Profile Constrained Baseline Constrained Baseline
Profile Compatibility Full Limited to stream from the H264-E-BPS/BPF, amd BIS cores
Additional Features not supported Interlaced with Main Profile Syntax
Throughput (cycles/pixel)



Silicon Resources1 Moderate Small


  1. Very Small <100k Gates, Moderate <500K Gates



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