- Options for one or two cycles per pixel
- UHD/4K and very high frame rates at lower resolutions in ASICs and FPGAs
- ISO/IEC 14496-10/ITU-T H.264 Constrained Baseline Profile specification
- Interlaced Video using Main Profile syntax
- Output Annex B NAL byte stream decodable by Baseline, Main, and High Profile decoders
Input Video Formats
- Progressive or Interlaced, 4:2:0 YCbCr input with 8 bits per color sample
- Up to UHD/4k in ASICs; up to Full-HD in FPGAs
- Optional multichannel encoding
Low Latency and Low Bit Rates with Fewer Artifacts
- Constant Bit-Rate (CBR) output for smaller stream buffers and end-to-end latency
- Advanced rate control regulates Qp multiple times within a frame, and rapidly responds to temporal or spatial video variations
- Enables artifacts-free Intra-Refresh to eliminate bit rate peaks of I frames
- Block skipping, Quantized coefficients thresholding, and in-loop deblocking filter improve quality at low bit rates
Small and Low Power
- 250K gates and 375 kbits of RAM (for two-cycles-per-pixel configutation)
- Uses less power than equally capable hardware H.264 encoders thanks to its smaller silicon footprint and small external memory bandwidth
- Consumes much less power than any equivalent software, or software-hardware encoder
Ease of Integration
- Zero CPU overhead, stand-alone operation
- Flexible external memory interface uses separate clock, is independent of memory type and tolerant to latencies
Call or click.
- H264-E-BPS Low-Power AVC/H.264 Baseline Profile Encoder Core
- H264-E-MPS Low-Power AVC/H.264 Main Profile Encoder Core
- H264-E-HIS Intra-Only High Profile Encoder Core
- H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core
- H264-LD-BP Low-Power AVC/H.264 Baseline Profile Decoder Core
- H265-MP-D HEVC/H.265 Main Profile Video Decoder
- H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem
- H264OIP-HDD H.264 Video Over IP – HD Decoder Subsystem
- Choosing the Right IP Cores for Low-Latency Video Streaming
- IoT Phase 2: Design Matters
- White Paper: Understanding—and Reducing—Latency in Video Compression Systems
See more H264 blog posts >>>
H264-E-BPFUltra-Fast AVC/H.264 Baseline Profile Encoder
The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an ultra-high throughput, UHD/4K capable hardware encoder that is optimized for ultra-low-latency video streaming at low bit rates.
The H264-E-BPF encoder requires less silicon area than most equally capable hardware H.264 encoders—approximately 250K gates—allowing for very cost-effective implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable high-throughput H.264 coding at an extremely low energy cost. The encoder is able to process UHD/4K video when mapped on modern ASIC technologies, and Full-HD when mapped on FPGAs.
Despite being small, the H264-E-BPF produces high-quality video, especially at low bit rates, and is suitable for systems with low latency requirements. It uses constant quantization to output video streams of Variable Bit-Rate (VBR), or automatically regulates quantization multiple times within a frame to output Constant Bit-Rate (CBR) streams. In CBR mode it responds rapidly to temporal or spatial changes in the video content. This can be combined with an artifacts-free Intra-Refresh coding implementation to effectively eliminate bit rate peaks, while preserving the periodic intra-coded references. As a result, the stream buffers can be smaller than those typically required, and the end-to-end latency can be brought down to frame or sub-frame levels. Video quality at low-bit rates is preserved, as the encoder intelligently uses block-skipping and quantization coefficient thresholding to reduce bit rate at minimal quality loss, and uses the in-loop deblocking filter to eliminate the blocking artifact.
The core was designed for ease of use and integration. Once initially programmed, it operates without any assistance from the host processor. The encoder’s memory interface is extremely flexible: it operates on a separate clock domain, is independent from the external memory type and memory controller, and is tolerant to large latencies. The core is optionally delivered with a raster-to-block converter, and wrappers for AMBA® AHB, AXI, or AXI-Streaming buses are available.
Customers can further decrease their time to market by using CAST’s integration services to receive complete video encoding subsystems. These integrate the encoder core with video and networking interface controllers, networking stacks, or other CAST or third-party IP cores.
The H264-E-BPF IP core is designed using with industry best practices and has been production proven multiple times. Its deliverables include a complete verification environment and a bit-accurate software model.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. Meanwhile, we provide the following representative results (each in a new pop-up window):
- Variable Bit-Rate with Constant Qp (VBR-CQP) and Constant Bit-Rate (CBR) output with CAVLC Encoding
- Efficient Inter- and Intra- Prediction
- Motion vector up to –16.00/+15.75 pixels down to ¼ pel accuracy
- All intra 16x16 and most intra 4x4 modes
- Options for improved error resilience
- Multiple slices per frame
- Intra-only coding
- Options for better quality at low bit-rates
- Block skipping
- Deblocking filter
- Separate quantization values for luma and chrome
- Thresholding of quantized transform coefficient
Silicon Resources Utilization
The H264-E-BPF core’s silicon resources requirements depend on its configuration. A two cycles per pixel configuration synthesizes to approximately 250K gates and 375 kbits of memory, and a one cycle per pixel configuration synthesizes to 400K gates and 600 kbits of memory.
The core is available in source-code HDL (Verilog or VHDL) or as a targeted netlist, and its deliverables include everything required for successful implementation:
- Source-code HDL (Verilog or VHDL) (ASICs) or as a targeted netlist (FPGAs)
- Sophisticated self-checking Testbench
- Synthesis scripts
- Simulation script, vectors and expected results
Software (C++) Bit-Accurate Model and test-vector generator
- Comprehensive user documentation
Potential customers can readily evaluate the video encoder’s compression efficiency can be evaluated by using:
- Available sample compressed video streams
- The available Bit-Accurate Model with your choice of input videos
- The Video over IP reference design with video captured over an HDMI interface
Please contact CAST to arrange for your evaluation preference.
H.264 Cores Family
The H264-E-BPS is one member of the family of H.264 encoder cores that CAST offers. The following table summarizes the family members and highlights their basic features.
Low Power Encoders
2 or 1
|ASIC (16nm) Performance||UHD/4k@30||UHD/4k@30||1080p60||1080p60||UHD/4k@60|
|Silicon Resources 1||Very Small||Small||Small||Moderate||Moderate–High|
|Main||High 10 Intra||Constrained
|Slices Types||IDR||IDR, P||IDR, P||IDR||IDR, P|
|Bits per sample||8||8||8||8, 10||8|
|Multiple video channels||Optional||Optional||Optional||Optional|
|CAVLC / CABAC||/||/||/||/||/|
|CBR and VBR|
- Very Small <100K Gates, Small <200K Gates, Moderate <500K Gates, and High >500K Gates.
|Profile||Constrained Baseline||Constrained Baseline|
|Profile Compatibility||Full||Limited to stream from the H264-E-BPS/BPF, amd BIS cores|
|Additional Features||Interlaced with Main Profile Syntax|
- Very Small <100k Gates, Moderate <500K Gates