H.264 IP Core H264-D H.264 Video Decoder Core
Implements a hardware video decoder compatible to Constrained Baseline Profile, Main Profile, or High 4:2:2 Profile of the H.264/AVC standard (also known as MPEG-4 Part 10).
The core can decode streams at the 4.1 level of the standard, which includes Full-HD, 1920x1080 video encoded at 50Mbits/second. Optional High 4:2:2 Profile supports decoding streams at rates up to 200 MBits/second.
The video decoder is designed for straightforward, trouble-free SoC integration. It operates on a stand-alone basis such that decoding proceeds without any assistance or input from the host processor. A standard AMBA® APB system bus interface gives the host real-time control and status access. A flexible memory interface for reading the incoming compressed video and storing the resulting decompressed video is independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture. Furthermore, the core’s decoded image storage can be configured to match the input video stream, allowing the minimum amount of memory to be allocated for each specific stream.
The core is designed for reuse and reliability, and has been rigorously verified and FPGA proven. A complete ‘C’ reference driver and fully documented API facilitate system integration. An optional FPGA-based reference system using the core provides a complete development environment for evaluation and early software development.
This core available in the second quarter of 2012. Please contact CAST sales for early info.
Download PDF datasheets for more info: coming soon
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